From 734ab17cb8e14a7fea3d7c522a6c3dd56a93dd2c Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 2 Jun 2016 21:01:40 +0000 Subject: [PATCH] Merging r258936: ------------------------------------------------------------------------ r258936 | thomas.stellard | 2016-01-27 07:53:52 -0800 (Wed, 27 Jan 2016) | 14 lines AMDGPU/SI: Fix commuting of 32-bit VOPC instructions Summary: We didn't have entries in the commuting table for the 32-bit instructions. I don't think we hit this problem now, but we will once uniform branching is enabled. Tests will come in a later commit. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16600 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271589 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.td | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index 8735277149a..f4e047c0b23 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -1788,7 +1788,8 @@ multiclass VOPC_m pattern, list sched, string revOpName = "", string asm = opName#"_e32 "#op_asm, string alias_asm = opName#" "#op_asm> { - def "" : VOPC_Pseudo { + def "" : VOPC_Pseudo , + VOP2_REV { let Defs = !if(DefExec, [VCC, EXEC], [VCC]); let SchedRW = sched; } @@ -1819,7 +1820,8 @@ multiclass VOPC_m pattern, multiclass VOPC_Helper pat32, list pat64, bit DefExec, string revOp, VOPProfile p, list sched> { - defm _e32 : VOPC_m ; + defm _e32 : VOPC_m ; defm _e64 : VOP3_C_m ; -- 2.50.1