From 724673be8359473b84222aa62cb0253738f9c06e Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 23 Mar 2017 15:20:05 +0800 Subject: [PATCH] soc: add apb_ctrl, struct headers for rtc_cntl and rtc_io --- components/esp32/include/soc/apb_ctrl_reg.h | 294 ++++++++++ .../esp32/include/soc/apb_ctrl_struct.h | 120 ++++ .../esp32/include/soc/rtc_cntl_struct.h | 553 ++++++++++++++++++ components/esp32/include/soc/rtc_io_struct.h | 280 +++++++++ components/esp32/include/soc/soc.h | 1 + 5 files changed, 1248 insertions(+) create mode 100644 components/esp32/include/soc/apb_ctrl_reg.h create mode 100644 components/esp32/include/soc/apb_ctrl_struct.h create mode 100644 components/esp32/include/soc/rtc_cntl_struct.h create mode 100644 components/esp32/include/soc/rtc_io_struct.h diff --git a/components/esp32/include/soc/apb_ctrl_reg.h b/components/esp32/include/soc/apb_ctrl_reg.h new file mode 100644 index 0000000000..2e5ea54c4c --- /dev/null +++ b/components/esp32/include/soc/apb_ctrl_reg.h @@ -0,0 +1,294 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_REG_H_ +#define _SOC_APB_CTRL_REG_H_ + +#include "soc.h" +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) +/* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_QUICK_CLK_CHNG (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_M (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_V 0x1 +#define APB_CTRL_QUICK_CLK_CHNG_S 13 +/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_V 0x1 +#define APB_CTRL_RST_TICK_CNT_S 12 +/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (BIT(11)) +#define APB_CTRL_CLK_EN_V 0x1 +#define APB_CTRL_CLK_EN_S 11 +/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (BIT(10)) +#define APB_CTRL_CLK_320M_EN_V 0x1 +#define APB_CTRL_CLK_320M_EN_S 10 +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define APB_CTRL_PRE_DIV_CNT 0x000003FF +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3FF +#define APB_CTRL_PRE_DIV_CNT_S 0 + +#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) +/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define APB_CTRL_XTAL_TICK_NUM 0x000000FF +#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) +#define APB_CTRL_XTAL_TICK_NUM_V 0xFF +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +#define APB_CTRL_PLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x8) +/* APB_CTRL_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */ +/*description: */ +#define APB_CTRL_PLL_TICK_NUM 0x000000FF +#define APB_CTRL_PLL_TICK_NUM_M ((APB_CTRL_PLL_TICK_NUM_V)<<(APB_CTRL_PLL_TICK_NUM_S)) +#define APB_CTRL_PLL_TICK_NUM_V 0xFF +#define APB_CTRL_PLL_TICK_NUM_S 0 + +#define APB_CTRL_CK8M_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0xC) +/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */ +/*description: */ +#define APB_CTRL_CK8M_TICK_NUM 0x000000FF +#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) +#define APB_CTRL_CK8M_TICK_NUM_V 0xFF +#define APB_CTRL_CK8M_TICK_NUM_S 0 + +#define APB_CTRL_APB_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x10) +/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data + is from GPIO matrix*/ +#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_M (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x1 +#define APB_CTRL_SARADC_DATA_TO_I2S_S 26 +/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data + in this case the resolution should not be larger than 11 bits.*/ +#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_M (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x1 +#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25 +/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x1 +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24 +/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x1 +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23 +/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000F +#define APB_CTRL_SARADC_SAR2_PATT_LEN_M ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S)) +#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0xF +#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19 +/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000F +#define APB_CTRL_SARADC_SAR1_PATT_LEN_M ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S)) +#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0xF +#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15 +/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ +/*description: SAR clock divider*/ +#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_CTRL_SARADC_SAR_CLK_DIV_M ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S)) +#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7 +/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6 +/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ +#define APB_CTRL_SARADC_SAR_SEL (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_M (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_V 0x1 +#define APB_CTRL_SARADC_SAR_SEL_S 5 +/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: single mode 1: double mode 2: alternate mode*/ +#define APB_CTRL_SARADC_WORK_MODE 0x00000003 +#define APB_CTRL_SARADC_WORK_MODE_M ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S)) +#define APB_CTRL_SARADC_WORK_MODE_V 0x3 +#define APB_CTRL_SARADC_WORK_MODE_S 3 +/* APB_CTRL_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled + by PWDET CTRL*/ +#define APB_CTRL_SARADC_SAR2_MUX (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_M (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_V 0x1 +#define APB_CTRL_SARADC_SAR2_MUX_S 2 +/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_START (BIT(1)) +#define APB_CTRL_SARADC_START_M (BIT(1)) +#define APB_CTRL_SARADC_START_V 0x1 +#define APB_CTRL_SARADC_START_S 1 +/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_START_FORCE (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_M (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_V 0x1 +#define APB_CTRL_SARADC_START_FORCE_S 0 + +#define APB_CTRL_APB_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x14) +/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ +#define APB_CTRL_SARADC_SAR2_INV (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_M (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_V 0x1 +#define APB_CTRL_SARADC_SAR2_INV_S 10 +/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ +#define APB_CTRL_SARADC_SAR1_INV (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_M (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_V 0x1 +#define APB_CTRL_SARADC_SAR1_INV_S 9 +/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ +/*description: max conversion number*/ +#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_CTRL_SARADC_MAX_MEAS_NUM_M ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S)) +#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1 +/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0 + +#define APB_CTRL_APB_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x18) +/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ +/*description: sample cycles*/ +#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000FF +#define APB_CTRL_SARADC_SAMPLE_CYCLE_M ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S)) +#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0xFF +#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24 +/* APB_CTRL_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */ +/*description: */ +#define APB_CTRL_SARADC_START_WAIT 0x000000FF +#define APB_CTRL_SARADC_START_WAIT_M ((APB_CTRL_SARADC_START_WAIT_V)<<(APB_CTRL_SARADC_START_WAIT_S)) +#define APB_CTRL_SARADC_START_WAIT_V 0xFF +#define APB_CTRL_SARADC_START_WAIT_S 16 +/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */ +/*description: */ +#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000FF +#define APB_CTRL_SARADC_STANDBY_WAIT_M ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S)) +#define APB_CTRL_SARADC_STANDBY_WAIT_V 0xFF +#define APB_CTRL_SARADC_STANDBY_WAIT_S 8 +/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ +/*description: */ +#define APB_CTRL_SARADC_RSTB_WAIT 0x000000FF +#define APB_CTRL_SARADC_RSTB_WAIT_M ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S)) +#define APB_CTRL_SARADC_RSTB_WAIT_V 0xFF +#define APB_CTRL_SARADC_RSTB_WAIT_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x1C) +/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x20) +/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x24) +/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x28) +/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x2C) +/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x30) +/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x34) +/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x38) +/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0 + +#define APB_CTRL_APLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x3C) +/* APB_CTRL_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */ +/*description: */ +#define APB_CTRL_APLL_TICK_NUM 0x000000FF +#define APB_CTRL_APLL_TICK_NUM_M ((APB_CTRL_APLL_TICK_NUM_V)<<(APB_CTRL_APLL_TICK_NUM_S)) +#define APB_CTRL_APLL_TICK_NUM_V 0xFF +#define APB_CTRL_APLL_TICK_NUM_S 0 + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x7C) +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define APB_CTRL_DATE 0xFFFFFFFF +#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) +#define APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_CTRL_DATE_S 0 + + + + +#endif /*_SOC_APB_CTRL_REG_H_ */ + + diff --git a/components/esp32/include/soc/apb_ctrl_struct.h b/components/esp32/include/soc/apb_ctrl_struct.h new file mode 100644 index 0000000000..d25967838a --- /dev/null +++ b/components/esp32/include/soc/apb_ctrl_struct.h @@ -0,0 +1,120 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_STRUCT_H_ +#define _SOC_APB_CTRL_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t pre_div: 10; + volatile uint32_t clk_320m_en: 1; + volatile uint32_t clk_en: 1; + volatile uint32_t rst_tick: 1; + volatile uint32_t quick_clk_chng: 1; + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }clk_conf; + union { + struct { + volatile uint32_t xtal_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }xtal_tick_conf; + union { + struct { + volatile uint32_t pll_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }pll_tick_conf; + union { + struct { + volatile uint32_t ck8m_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }ck8m_tick_conf; + union { + struct { + volatile uint32_t start_force: 1; + volatile uint32_t start: 1; + volatile uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/ + volatile uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ + volatile uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ + volatile uint32_t sar_clk_gated: 1; + volatile uint32_t sar_clk_div: 8; /*SAR clock divider*/ + volatile uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + volatile uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + volatile uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + volatile uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ + volatile uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ + volatile uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ + volatile uint32_t reserved27: 5; + }; + volatile uint32_t val; + }saradc_ctrl; + union { + struct { + volatile uint32_t meas_num_limit: 1; + volatile uint32_t max_meas_num: 8; /*max conversion number*/ + volatile uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ + volatile uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ + volatile uint32_t reserved11: 21; + }; + volatile uint32_t val; + }saradc_ctrl2; + union { + struct { + volatile uint32_t rstb_wait: 8; + volatile uint32_t standby_wait: 8; + volatile uint32_t start_wait: 8; + volatile uint32_t sample_cycle: 8; /*sample cycles*/ + }; + volatile uint32_t val; + }saradc_fsm; + volatile uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/ + union { + struct { + volatile uint32_t apll_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }apll_tick_conf; + volatile uint32_t reserved_40; + volatile uint32_t reserved_44; + volatile uint32_t reserved_48; + volatile uint32_t reserved_4c; + volatile uint32_t reserved_50; + volatile uint32_t reserved_54; + volatile uint32_t reserved_58; + volatile uint32_t reserved_5c; + volatile uint32_t reserved_60; + volatile uint32_t reserved_64; + volatile uint32_t reserved_68; + volatile uint32_t reserved_6c; + volatile uint32_t reserved_70; + volatile uint32_t reserved_74; + volatile uint32_t reserved_78; + volatile uint32_t date; /**/ +} apb_ctrl_dev_t; + +#endif /* _SOC_APB_CTRL_STRUCT_H_ */ diff --git a/components/esp32/include/soc/rtc_cntl_struct.h b/components/esp32/include/soc/rtc_cntl_struct.h new file mode 100644 index 0000000000..acb12432b0 --- /dev/null +++ b/components/esp32/include/soc/rtc_cntl_struct.h @@ -0,0 +1,553 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_CNTL_STRUCT_H_ +#define _SOC_RTC_CNTL_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd: 1; /*crystall force power down*/ + uint32_t xtl_force_pu: 1; /*crystall force power up*/ + uint32_t bias_sleep_folw_8m: 1; /*BIAS_SLEEP follow CK8M*/ + uint32_t bias_force_sleep: 1; /*BIAS_SLEEP force sleep*/ + uint32_t bias_force_nosleep: 1; /*BIAS_SLEEP force no sleep*/ + uint32_t bias_i2c_folw_8m: 1; /*BIAS_I2C follow CK8M*/ + uint32_t bias_i2c_force_pd: 1; /*BIAS_I2C force power down*/ + uint32_t bias_i2c_force_pu: 1; /*BIAS_I2C force power up*/ + uint32_t bias_core_folw_8m: 1; /*BIAS_CORE follow CK8M*/ + uint32_t bias_core_force_pd: 1; /*BIAS_CORE force power down*/ + uint32_t bias_core_force_pu: 1; /*BIAS_CORE force power up*/ + uint32_t xtl_force_iso: 1; + uint32_t pll_force_iso: 1; + uint32_t analog_force_iso: 1; + uint32_t xtl_force_noiso: 1; + uint32_t pll_force_noiso: 1; + uint32_t analog_force_noiso: 1; + uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst: 1; /*SW system reset*/ + }; + uint32_t val; + } options0; + uint32_t slp_timer0; /*RTC sleep timer low 32 bits*/ + union { + struct { + uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } slp_timer1; + union { + struct { + uint32_t reserved0: 30; + uint32_t valid: 1; /*To indicate the register is updated*/ + uint32_t update: 1; /*Set 1: to update register with RTC timer*/ + }; + uint32_t val; + } time_update; + uint32_t time0; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t time_hi:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time1; + union { + struct { + uint32_t reserved0: 20; + uint32_t touch_wakeup_force_en: 1; /*touch controller force wake up*/ + uint32_t ulp_cp_wakeup_force_en: 1; /*ULP-coprocessor force wake up*/ + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/ + uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ + uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ + uint32_t reserved25: 3; + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*sleep wakeup bit*/ + uint32_t slp_reject: 1; /*sleep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ + }; + uint32_t val; + } state0; + union { + struct { + uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ + }; + uint32_t val; + } timer1; + union { + struct { + uint32_t reserved0: 15; + uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ + uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + }; + uint32_t val; + } timer2; + union { + struct { + uint32_t wifi_wait_timer: 9; + uint32_t wifi_powerup_timer: 7; + uint32_t rom_ram_wait_timer: 9; + uint32_t rom_ram_powerup_timer: 7; + }; + uint32_t val; + } timer3; + union { + struct { + uint32_t rtc_wait_timer: 9; + uint32_t rtc_powerup_timer: 7; + uint32_t dg_wrap_wait_timer: 9; + uint32_t dg_wrap_powerup_timer: 7; + }; + uint32_t val; + } timer4; + union { + struct { + uint32_t ulp_cp_subtimer_prediv: 8; + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t rtcmem_wait_timer: 9; + uint32_t rtcmem_powerup_timer: 7; + }; + uint32_t val; + } timer5; + union { + struct { + uint32_t reserved0: 23; + uint32_t plla_force_pd: 1; /*PLLA force power down*/ + uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu: 1; /*1: PVTMON power up otherwise power down*/ + uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up otherwise power down*/ + uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up otherwise power down*/ + uint32_t reserved29: 1; + uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up otherwise power down*/ + uint32_t pll_i2c_pu: 1; /*1: PLL_I2C power up otherwise power down*/ + }; + uint32_t val; + } ana_conf; + union { + struct { + uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ + uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/ + uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } reset_state; + union { + struct { + uint32_t wakeup_cause: 11; /*wakeup cause*/ + uint32_t rtc_wakeup_ena: 11; /*wakeup enable bitmap*/ + uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } wakeup_state; + union { + struct { + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/ + uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch: 1; /*enable touch interrupt*/ + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/ + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ + uint32_t rtc_touch: 1; /*touch interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/ + uint32_t rtc_sar: 1; /*ULP-coprocessor interrupt state*/ + uint32_t rtc_touch: 1; /*touch interrupt state*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/ + uint32_t rtc_sar: 1; /*Clear ULP-coprocessor interrupt state*/ + uint32_t rtc_touch: 1; /*Clear touch interrupt state*/ + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_clr; + uint32_t rtc_store0; /*32-bit general purpose retention register*/ + uint32_t rtc_store1; /*32-bit general purpose retention register*/ + uint32_t rtc_store2; /*32-bit general purpose retention register*/ + uint32_t rtc_store3; /*32-bit general purpose retention register*/ + union { + struct { + uint32_t reserved0: 30; + uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/ + uint32_t ctr_en: 1; /*enable control XTAL by external pads*/ + }; + uint32_t val; + } ext_xtl_conf; + union { + struct { + uint32_t reserved0: 30; + uint32_t wakeup0_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ + uint32_t wakeup1_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ + }; + uint32_t val; + } ext_wakeup_conf; + union { + struct { + uint32_t reserved0: 24; + uint32_t gpio_reject_en: 1; /*enable GPIO reject*/ + uint32_t sdio_reject_en: 1; /*enable SDIO reject*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ + uint32_t reject_cause: 4; /*sleep reject cause*/ + }; + uint32_t val; + } slp_reject_conf; + union { + struct { + uint32_t reserved0: 29; + uint32_t cpusel_conf: 1; /*CPU sel option*/ + uint32_t cpuperiod_sel: 2; /*CPU period sel*/ + }; + uint32_t val; + } cpu_period_conf; + union { + struct { + uint32_t reserved0: 22; + uint32_t sdio_act_dnum:10; + }; + uint32_t val; + } sdio_act_conf; + union { + struct { + uint32_t reserved0: 4; + uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ + uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t ck8m_dfreq_force: 1; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t soc_clk_sel: 2; /*SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ + uint32_t ana_clk_rtc_sel: 2; /*slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reserved0: 21; + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio: 1; /*SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ + }; + uint32_t val; + } sdio_conf; + union { + struct { + uint32_t reserved0: 24; + uint32_t dbg_atten: 2; /*DBG_ATTEN*/ + uint32_t enb_sck_xtal: 1; /*ENB_SCK_XTAL*/ + uint32_t inc_heartbeat_refresh: 1; /*INC_HEARTBEAT_REFRESH*/ + uint32_t dec_heartbeat_period: 1; /*DEC_HEARTBEAT_PERIOD*/ + uint32_t inc_heartbeat_period: 1; /*INC_HEARTBEAT_PERIOD*/ + uint32_t dec_heartbeat_width: 1; /*DEC_HEARTBEAT_WIDTH*/ + uint32_t rst_bias_i2c: 1; /*RST_BIAS_I2C*/ + }; + uint32_t val; + } bias_conf; + union { + struct { + uint32_t reserved0: 7; + uint32_t sck_dcap_force: 1; /*N/A*/ + uint32_t dig_dbias_slp: 3; /*DIG_REG_DBIAS during sleep*/ + uint32_t dig_dbias_wak: 3; /*DIG_REG_DBIAS during wakeup*/ + uint32_t sck_dcap: 8; /*SCK_DCAP*/ + uint32_t rtc_dbias_slp: 3; /*RTC_DBIAS during sleep*/ + uint32_t rtc_dbias_wak: 3; /*RTC_DBIAS during wakeup*/ + uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ + uint32_t rtc_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtc_force_pu: 1; /*RTC_REG force power up*/ + }; + uint32_t val; + } rtc; + union { + struct { + uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/ + uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/ + uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/ + uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/ + uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/ + uint32_t force_noiso: 1; /*rtc_peri force no ISO*/ + uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine*/ + uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/ + uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/ + uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ + uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/ + uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/ + uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/ + uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/ + uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/ + uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/ + uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/ + uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/ + uint32_t pwc_force_pd: 1; /*rtc_peri force power down*/ + uint32_t pwc_force_pu: 1; /*rtc_peri force power up*/ + uint32_t pd_en: 1; /*enable power down rtc_peri in sleep*/ + uint32_t reserved21: 11; + }; + uint32_t val; + } rtc_pwc; + union { + struct { + uint32_t reserved0: 3; + uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ + uint32_t rom0_force_pd: 1; /*ROM force power down*/ + uint32_t rom0_force_pu: 1; /*ROM force power up*/ + uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/ + uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/ + uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/ + uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/ + uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/ + uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/ + uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/ + uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/ + uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/ + uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/ + uint32_t wifi_force_pd: 1; /*wifi force power down*/ + uint32_t wifi_force_pu: 1; /*wifi force power up*/ + uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ + uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ + uint32_t reserved21: 3; + uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/ + uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/ + uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/ + uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/ + uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/ + uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/ + uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en: 1; /*enable power down digital core in sleep*/ + }; + uint32_t val; + } dig_pwc; + union { + struct { + uint32_t reserved0: 7; + uint32_t dig_iso_force_off: 1; + uint32_t dig_iso_force_on: 1; + uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ + uint32_t rom0_force_iso: 1; /*ROM force ISO*/ + uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/ + uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/ + uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/ + uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/ + uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/ + uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/ + uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/ + uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/ + uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/ + uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/ + uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/ + uint32_t wifi_force_iso: 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso: 1; /*digital core force no ISO*/ + }; + uint32_t val; + } dig_iso; + union { + struct { + uint32_t reserved0: 7; + uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length: 3; /*system reset counter length*/ + uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ + uint32_t level_int_en: 1; /*N/A*/ + uint32_t edge_int_en: 1; /*N/A*/ + uint32_t stg3: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg2: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg1: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg0: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t en: 1; /*enable RTC WDT*/ + }; + uint32_t val; + } wdt_config0; + uint32_t wdt_config1; /**/ + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ + union { + struct { + uint32_t reserved0: 31; + uint32_t feed: 1; + }; + uint32_t val; + } wdt_feed; + uint32_t wdt_wprotect; /**/ + union { + struct { + uint32_t reserved0: 29; + uint32_t ent_rtc: 1; /*ENT_RTC*/ + uint32_t dtest_rtc: 2; /*DTEST_RTC*/ + }; + uint32_t val; + } test_mux; + union { + struct { + uint32_t reserved0: 20; + uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t procpu_c1: 6; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + }; + uint32_t val; + } sw_cpu_stall; + uint32_t store4; /*32-bit general purpose retention register*/ + uint32_t store5; /*32-bit general purpose retention register*/ + uint32_t store6; /*32-bit general purpose retention register*/ + uint32_t store7; /*32-bit general purpose retention register*/ + uint32_t diag0; /**/ + uint32_t diag1; /**/ + union { + struct { + uint32_t adc1_hold_force: 1; + uint32_t adc2_hold_force: 1; + uint32_t pdac1_hold_force: 1; + uint32_t pdac2_hold_force: 1; + uint32_t sense1_hold_force: 1; + uint32_t sense2_hold_force: 1; + uint32_t sense3_hold_force: 1; + uint32_t sense4_hold_force: 1; + uint32_t touch_pad0_hold_force: 1; + uint32_t touch_pad1_hold_force: 1; + uint32_t touch_pad2_hold_force: 1; + uint32_t touch_pad3_hold_force: 1; + uint32_t touch_pad4_hold_force: 1; + uint32_t touch_pad5_hold_force: 1; + uint32_t touch_pad6_hold_force: 1; + uint32_t touch_pad7_hold_force: 1; + uint32_t x32p_hold_force: 1; + uint32_t x32n_hold_force: 1; + uint32_t reserved18: 14; + }; + uint32_t val; + } hold_force; + union { + struct { + uint32_t ext_wakeup1_sel: 18; /*Bitmap to select RTC pads for ext wakeup1*/ + uint32_t ext_wakeup1_status_clr: 1; /*clear ext wakeup1 status*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } ext_wakeup1; + union { + struct { + uint32_t ext_wakeup1_status:18; /*ext wakeup1 status*/ + uint32_t reserved18: 14; + }; + uint32_t val; + } ext_wakeup1_status; + union { + struct { + uint32_t reserved0: 14; + uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait: 10; /*brown out reset wait cycles*/ + uint32_t rst_ena: 1; /*enable brown out reset*/ + uint32_t thres: 3; /*brown out threshold*/ + uint32_t ena: 1; /*enable brown out*/ + uint32_t det: 1; /*brown out detect*/ + }; + uint32_t val; + } brown_out; + uint32_t reserved_39; + uint32_t reserved_3d; + uint32_t reserved_41; + uint32_t reserved_45; + uint32_t reserved_49; + uint32_t reserved_4d; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_cntl_dev_t; +#endif /* _SOC_RTC_CNTL_STRUCT_H_ */ diff --git a/components/esp32/include/soc/rtc_io_struct.h b/components/esp32/include/soc/rtc_io_struct.h new file mode 100644 index 0000000000..da27078c8e --- /dev/null +++ b/components/esp32/include/soc/rtc_io_struct.h @@ -0,0 +1,280 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_IO_STRUCT_H_ +#define _SOC_RTC_IO_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t reserved0: 14; + uint32_t data:18; /*GPIO0~17 output value*/ + }; + uint32_t val; + } out; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 output value write 1 to set*/ + }; + uint32_t val; + } out_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 output value write 1 to clear*/ + }; + uint32_t val; + } out_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t enable:18; /*GPIO0~17 output enable*/ + }; + uint32_t val; + } enable; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 output enable write 1 to set*/ + }; + uint32_t val; + } enable_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 output enable write 1 to clear*/ + }; + uint32_t val; + } enable_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t status:18; /*GPIO0~17 interrupt status*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 interrupt status write 1 to set*/ + }; + uint32_t val; + } status_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 interrupt status write 1 to clear*/ + }; + uint32_t val; + } status_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t in:18; /*GPIO0~17 input value*/ + }; + uint32_t val; + } in_val; + union { + struct { + uint32_t reserved0: 2; + uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + uint32_t reserved11: 21; + }; + uint32_t val; + } pin[18]; + union { + struct { + uint32_t sel0: 5; + uint32_t sel1: 5; + uint32_t sel2: 5; + uint32_t sel3: 5; + uint32_t sel4: 5; + uint32_t no_gating_12m: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } debug_sel; + uint32_t dig_pad_hold; /*select the digital pad hold value.*/ + union { + struct { + uint32_t reserved0: 30; + uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ + uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ + }; + uint32_t val; + } hall_sens; + union { + struct { + uint32_t reserved0: 4; + uint32_t sense4_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense4_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense4_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense4_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense3_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense3_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense3_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense3_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense2_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense2_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense2_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense2_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense1_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense1_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense1_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense1_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense4_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense3_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense2_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense1_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense4_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense3_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense2_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense1_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } sensor_pads; + union { + struct { + uint32_t reserved0: 18; + uint32_t adc2_fun_ie: 1; /*the input enable of the pad*/ + uint32_t adc2_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t adc2_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t adc2_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t adc1_fun_ie: 1; /*the input enable of the pad*/ + uint32_t adc1_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t adc1_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t adc1_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t adc2_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t adc1_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t adc2_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t adc1_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } adc_pad; + union { + struct { + uint32_t reserved0: 10; + uint32_t dac_xpd_force: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ + uint32_t fun_ie: 1; /*the input enable of the pad*/ + uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd_dac: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ + uint32_t dac: 8; /*PAD DAC1 control code.*/ + uint32_t rue: 1; /*the pull up enable of the pad*/ + uint32_t rde: 1; /*the pull down enable of the pad*/ + uint32_t hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t drv: 2; /*the driver strength of the pad*/ + }; + uint32_t val; + } pad_dac[2]; + union { + struct { + uint32_t reserved0: 1; + uint32_t dbias_xtal_32k: 2; /*32K XTAL self-bias reference control.*/ + uint32_t dres_xtal_32k: 2; /*32K XTAL resistor bias control.*/ + uint32_t x32p_fun_ie: 1; /*the input enable of the pad*/ + uint32_t x32p_slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t x32p_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t x32p_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t x32p_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t x32n_fun_ie: 1; /*the input enable of the pad*/ + uint32_t x32n_slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t x32n_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t x32n_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t x32n_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t x32p_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t x32n_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd_xtal_32k: 1; /*Power up 32kHz crystal oscillator*/ + uint32_t dac_xtal_32k: 2; /*32K XTAL bias current DAC.*/ + uint32_t x32p_rue: 1; /*the pull up enable of the pad*/ + uint32_t x32p_rde: 1; /*the pull down enable of the pad*/ + uint32_t x32p_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t x32p_drv: 2; /*the driver strength of the pad*/ + uint32_t x32n_rue: 1; /*the pull up enable of the pad*/ + uint32_t x32n_rde: 1; /*the pull down enable of the pad*/ + uint32_t x32n_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t x32n_drv: 2; /*the driver strength of the pad*/ + }; + uint32_t val; + } xtal_32k_pad; + union { + struct { + uint32_t reserved0: 23; + uint32_t dcur: 2; /*touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available*/ + uint32_t drange: 2; /*touch sensor saw wave voltage range.*/ + uint32_t drefl: 2; /*touch sensor saw wave bottom voltage.*/ + uint32_t drefh: 2; /*touch sensor saw wave top voltage.*/ + uint32_t xpd_bias: 1; /*touch sensor bias power on.*/ + }; + uint32_t val; + } touch_cfg; + union { + struct { + uint32_t reserved0: 12; + uint32_t to_gpio: 1; /*connect the rtc pad input to digital pad input �0� is availbale GPIO4*/ + uint32_t fun_ie: 1; /*the input enable of the pad*/ + uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd: 1; /*touch sensor power on.*/ + uint32_t tie_opt: 1; /*default touch sensor tie option. 0: tie low 1: tie high.*/ + uint32_t start: 1; /*start touch sensor.*/ + uint32_t dac: 3; /*touch sensor slope control. 3-bit for each touch panel default 100.*/ + uint32_t reserved26: 1; + uint32_t rue: 1; /*the pull up enable of the pad*/ + uint32_t rde: 1; /*the pull down enable of the pad*/ + uint32_t drv: 2; /*the driver strength of the pad*/ + uint32_t hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } touch_pad[10]; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select the wakeup source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/ + }; + uint32_t val; + } ext_wakeup0; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select the external xtl power source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/ + }; + uint32_t val; + } xtl_ext_ctr; + union { + struct { + uint32_t reserved0: 23; + uint32_t debug_bit_sel: 5; + uint32_t scl_sel: 2; /*�0� using TOUCH_PAD[0] as i2c clk �1� using TOUCH_PAD[2] as i2c clk*/ + uint32_t sda_sel: 2; /*�0� using TOUCH_PAD[1] as i2c sda �1� using TOUCH_PAD[3] as i2c sda*/ + }; + uint32_t val; + } sar_i2c_io; + union { + struct { + uint32_t date: 28; /*date*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_io_dev_t; +#endif /* _SOC_RTC_IO_STRUCT_H_ */ diff --git a/components/esp32/include/soc/soc.h b/components/esp32/include/soc/soc.h index 9b0c82fc1c..c17df3858c 100755 --- a/components/esp32/include/soc/soc.h +++ b/components/esp32/include/soc/soc.h @@ -184,6 +184,7 @@ #define DR_REG_TIMERGROUP1_BASE 0x3ff60000 #define DR_REG_SPI2_BASE 0x3ff64000 #define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_APB_CTRL_BASE 0x3ff66000 #define DR_REG_I2C1_EXT_BASE 0x3ff67000 #define DR_REG_SDMMC_BASE 0x3ff68000 #define DR_REG_EMAC_BASE 0x3ff69000 -- 2.40.0