From 70c6728fba514c1e41b48547911b554d0afe71e9 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 18 Sep 2017 13:32:33 +0000
Subject: [PATCH] [X86][SSE] Add vselect with zero tests (PR28925)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313529 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/vselect-zero.ll | 67 ++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 test/CodeGen/X86/vselect-zero.ll

diff --git a/test/CodeGen/X86/vselect-zero.ll b/test/CodeGen/X86/vselect-zero.ll
new file mode 100644
index 00000000000..5a1d118ee6e
--- /dev/null
+++ b/test/CodeGen/X86/vselect-zero.ll
@@ -0,0 +1,67 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2   | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx    | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2   | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+
+; PR28925
+
+define <4 x i32> @test1(<4 x i1> %cond, <4 x i32> %x) {
+; SSE2-LABEL: test1:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pslld $31, %xmm0
+; SSE2-NEXT:    psrad $31, %xmm0
+; SSE2-NEXT:    pandn %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: test1:
+; SSE42:       # BB#0:
+; SSE42-NEXT:    pslld $31, %xmm0
+; SSE42-NEXT:    xorps %xmm2, %xmm2
+; SSE42-NEXT:    blendvps %xmm0, %xmm2, %xmm1
+; SSE42-NEXT:    movaps %xmm1, %xmm0
+; SSE42-NEXT:    retq
+;
+; AVX-LABEL: test1:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpslld $31, %xmm0, %xmm0
+; AVX-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; AVX-NEXT:    retq
+  %r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %x) {
+; SSE-LABEL: test2:
+; SSE:       # BB#0:
+; SSE-NEXT:    cmpneqps %xmm1, %xmm0
+; SSE-NEXT:    andps %xmm2, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: test2:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcmpneqps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vandps %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %cond = fcmp oeq <4 x float> %a, %b
+  %r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
+  ret <4 x i32> %r
+}
+
+define float @fsel(float %a, float %b, float %x) {
+; SSE-LABEL: fsel:
+; SSE:       # BB#0:
+; SSE-NEXT:    cmpeqss %xmm1, %xmm0
+; SSE-NEXT:    andnps %xmm2, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: fsel:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcmpeqss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vandnps %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %cond = fcmp oeq float %a, %b
+  %sel = select i1 %cond, float 0.0, float %x
+  ret float %sel
+}
-- 
2.40.0