From 7074daff3e57f344201892f12166c55f32986e7b Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic <nemanja.i.ibm@gmail.com>
Date: Tue, 25 Jun 2019 10:46:13 +0000
Subject: [PATCH] [PowerPC] Emit XXSEL for vec_sel and code that has the same
 pattern

As pointed out in https://bugs.llvm.org/show_bug.cgi?id=41777
we do not emit a vector select even when the pretty much asks for one.
This patch changes that.

Differential revision: https://reviews.llvm.org/D61658


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364289 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCInstrVSX.td  |  4 ++
 test/CodeGen/PowerPC/vec-select.ll | 72 ++++++++++++++++++++++++++++++
 2 files changed, 76 insertions(+)
 create mode 100644 test/CodeGen/PowerPC/vec-select.ll

diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td
index 47323b77775..2529ecfb33f 100644
--- a/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/lib/Target/PowerPC/PPCInstrVSX.td
@@ -971,6 +971,10 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
 
 def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
           (v4i32 (XXLNOR $A, $A))>;
+def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A),
+                     (and v4i32:$B, v4i32:$C))),
+          (v4i32 (XXSEL $A, $B, $C))>;
+
 let Predicates = [IsBigEndian] in {
 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
           (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
diff --git a/test/CodeGen/PowerPC/vec-select.ll b/test/CodeGen/PowerPC/vec-select.ll
new file mode 100644
index 00000000000..152f4eebec1
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec-select.ll
@@ -0,0 +1,72 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
+define dso_local <4 x i32> @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <4 x i32> %c, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and.i = and <4 x i32> %neg.i, %a
+  %and1.i = and <4 x i32> %c, %b
+  %or.i = or <4 x i32> %and1.i, %and.i
+  ret <4 x i32> %or.i
+}
+
+define dso_local <8 x i16> @test2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <8 x i16> %c, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %and.i = and <8 x i16> %a, %neg.i
+  %and1.i = and <8 x i16> %c, %b
+  %or.i = or <8 x i16> %and.i, %and1.i
+  ret <8 x i16> %or.i
+}
+
+define dso_local <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <16 x i8> %c, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %and.i = and <16 x i8> %neg.i, %a
+  %and1.i = and <16 x i8> %c, %b
+  %or.i = or <16 x i8> %and.i, %and1.i
+  ret <16 x i8> %or.i
+}
+
+define dso_local <2 x i64> @test4(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <2 x i64> %c, <i64 -1, i64 -1>
+  %and.i = and <2 x i64> %a, %neg.i
+  %and1.i = and <2 x i64> %c, %b
+  %or.i = or <2 x i64> %and.i, %and1.i
+  ret <2 x i64> %or.i
+}
+
+; Not valid to emit XXSEL for this illegal type.
+define dso_local <4 x i1> @test5(<4 x i1> %a, <4 x i1> %b, <4 x i1> %c) {
+; CHECK-LABEL: test5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vspltisw v5, 1
+; CHECK-NEXT:    xxland vs0, vs36, vs35
+; CHECK-NEXT:    xxlxor vs1, vs36, vs37
+; CHECK-NEXT:    xxland vs1, vs34, vs1
+; CHECK-NEXT:    xxlor vs34, vs1, vs0
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <4 x i1> %c, <i1 -1, i1 -1, i1 -1, i1 -1>
+  %and.i = and <4 x i1> %a, %neg.i
+  %and1.i = and <4 x i1> %c, %b
+  %or.i = or <4 x i1> %and.i, %and1.i
+  ret <4 x i1> %or.i
+}
-- 
2.40.0