From 6f4bd04ecc5ab72a5363ffc17d9b7b7d5ec68a37 Mon Sep 17 00:00:00 2001
From: Diana Picus <diana.picus@linaro.org>
Date: Tue, 5 Feb 2019 10:21:37 +0000
Subject: [PATCH] [ARM GlobalISel] Support G_GEP for Thumb2

Same as ARM, but use a different opcode in the instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353151 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstructionSelector.cpp     |  2 +-
 lib/Target/ARM/ARMLegalizerInfo.cpp           |  4 +--
 .../GlobalISel/arm-legalize-load-store.mir    | 27 ++++++++++++++++
 test/CodeGen/ARM/GlobalISel/arm-legalizer.mir | 27 ----------------
 .../GlobalISel/thumb-select-load-store.mir    | 32 +++++++++++++++++++
 5 files changed, 62 insertions(+), 30 deletions(-)

diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp
index e5c0a07ab95..2d80a193b03 100644
--- a/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -930,7 +930,7 @@ bool ARMInstructionSelector::select(MachineInstr &I,
     return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
   }
   case G_GEP:
-    I.setDesc(TII.get(ARM::ADDrr));
+    I.setDesc(TII.get(STI.isThumb2() ? ARM::t2ADDrr : ARM::ADDrr));
     MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
     break;
   case G_FRAME_INDEX:
diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp
index ec404e07a5f..fb7053c8c00 100644
--- a/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -131,6 +131,8 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
               {s32, p0, 32},
               {p0, p0, 32}});
 
+  getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
+
   if (ST.isThumb()) {
     // FIXME: merge with the code for non-Thumb.
     computeTables();
@@ -161,8 +163,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
         .clampScalar(0, s32, s32);
   }
 
-  getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
-
   getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0},
                                                                  {s1});
 
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
index a955af9a97f..a3b4fece523 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
@@ -2,6 +2,8 @@
 # RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
 --- |
   define void @test_legal_loads_stores() { ret void }
+
+  define void @test_gep() { ret void }
 ...
 ---
 name:            test_legal_loads_stores
@@ -47,3 +49,28 @@ body:             |
     G_STORE %6(p0), %0(p0) :: (store 4)
     BX_RET 14, $noreg
 ...
+---
+name:            test_gep
+# CHECK-LABEL: name: test_gep
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(p0) = COPY $r0
+    %1(s32) = COPY $r1
+
+    ; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
+    %2(p0) = G_GEP %0, %1(s32)
+
+    $r0 = COPY %2(p0)
+    BX_RET 14, $noreg, implicit $r0
+...
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index cba996b1d86..4d49f25d94f 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -3,8 +3,6 @@
   define void @test_load_from_stack() { ret void }
   define void @test_load_store_64() #0 { ret void }
 
-  define void @test_gep() { ret void }
-
   define void @test_constants_s64() { ret void }
 
   define void @test_icmp_s8() { ret void }
@@ -85,31 +83,6 @@ body:             |
     BX_RET 14, $noreg
 ...
 ---
-name:            test_gep
-# CHECK-LABEL: name: test_gep
-legalized:       false
-# CHECK: legalized: true
-regBankSelected: false
-selected:        false
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0:
-    liveins: $r0, $r1
-
-    %0(p0) = COPY $r0
-    %1(s32) = COPY $r1
-
-    ; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
-    %2(p0) = G_GEP %0, %1(s32)
-
-    $r0 = COPY %2(p0)
-    BX_RET 14, $noreg, implicit $r0
-...
----
 name:            test_constants_s64
 # CHECK-LABEL: name: test_constants_s64
 legalized:       false
diff --git a/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir b/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
index 170c26e996c..ec64c8a2c1e 100644
--- a/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
+++ b/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
@@ -3,6 +3,8 @@
   define void @test_s8() { ret void }
   define void @test_s16() { ret void }
   define void @test_s32() { ret void }
+
+  define void @test_gep() { ret void }
 ...
 ---
 name:            test_s8
@@ -82,3 +84,33 @@ body:             |
     BX_RET 14, $noreg
     ; CHECK: BX_RET 14, $noreg
 ...
+---
+name:            test_gep
+# CHECK-LABEL: name: test_gep
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(p0) = COPY $r0
+    ; CHECK: [[PTR:%[0-9]+]]:gprnopc = COPY $r0
+
+    %1(s32) = COPY $r1
+    ; CHECK: [[OFF:%[0-9]+]]:rgpr = COPY $r1
+
+    %2(p0) = G_GEP %0, %1(s32)
+    ; CHECK: [[GEP:%[0-9]+]]:gprnopc = t2ADDrr [[PTR]], [[OFF]], 14, $noreg, $noreg
+
+    $r0 = COPY %2(p0)
+    ; CHECK: $r0 = COPY [[GEP]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
-- 
2.50.1