From 6eaaf637f4b983c73747668171c48fb91948ea8a Mon Sep 17 00:00:00 2001
From: Quentin Colombet <qcolombet@apple.com>
Date: Tue, 27 Sep 2016 22:55:04 +0000
Subject: [PATCH] [AArch64][RegisterBankInfo] Switch to statically allocated
 ValueMapping.

Another step toward TableGen'ed like structure for the RegisterBankInfo
of AArch64. By doing this, we also save a bit of compile time for the
exact same output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282550 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../AArch64/AArch64GenRegisterBankInfo.def    | 19 +++++++++++++++++++
 .../AArch64/AArch64RegisterBankInfo.cpp       | 15 +++++----------
 2 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/lib/Target/AArch64/AArch64GenRegisterBankInfo.def b/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
index 2183e4a3dc7..de85b383b63 100644
--- a/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
+++ b/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
@@ -65,5 +65,24 @@ RegisterBankInfo::PartialMapping PartMappings[] {
   {0, 512, FPRRegBank}
 };
 
+// ValueMappings.
+RegisterBankInfo::ValueMapping ValMappings[] {
+  /* BreakDown, NumBreakDowns */
+  // 0: GPR 32-bit value.
+  {&PartMappings[0], 1},
+  // 1: GPR 64-bit value.
+  {&PartMappings[1], 1},
+  // 2: FPR 32-bit value.
+  {&PartMappings[2], 1},
+  // 3: FPR 64-bit value.
+  {&PartMappings[3], 1},
+  // 4: FPR 128-bit value.
+  {&PartMappings[4], 1},
+  // 5: FPR 256-bit value.
+  {&PartMappings[5], 1},
+  // 6: FPR 512-bit value.
+  {&PartMappings[6], 1}
+};
+
 } // End AArch64 namespace.
 } // End llvm namespace.
diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index de66c817bc0..6315edd1743 100644
--- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -205,15 +205,11 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
     InstructionMapping FPRMapping(/*ID*/ 2, /*Cost*/ 1, /*NumOperands*/ 3);
     for (unsigned Idx = 0; Idx != 3; ++Idx) {
       GPRMapping.setOperandMapping(
-          Idx, getValueMapping(
-                   &AArch64::PartMappings[AArch64::getRegBankBaseIdx(Size) +
-                                          AArch64::FirstGPR],
-                   1));
+          Idx, AArch64::ValMappings[AArch64::getRegBankBaseIdx(Size) +
+                                    AArch64::FirstGPR]);
       FPRMapping.setOperandMapping(
-          Idx, getValueMapping(
-                   &AArch64::PartMappings[AArch64::getRegBankBaseIdx(Size) +
-                                          AArch64::FirstFPR],
-                   1));
+          Idx, AArch64::ValMappings[AArch64::getRegBankBaseIdx(Size) +
+                                    AArch64::FirstFPR]);
     }
     AltMappings.emplace_back(std::move(GPRMapping));
     AltMappings.emplace_back(std::move(FPRMapping));
@@ -324,8 +320,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   // Finally construct the computed mapping.
   for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
     if (MI.getOperand(Idx).isReg())
-      Mapping.setOperandMapping(
-          Idx, getValueMapping(&AArch64::PartMappings[OpFinalIdx[Idx]], 1));
+      Mapping.setOperandMapping(Idx, AArch64::ValMappings[OpFinalIdx[Idx]]);
 
   return Mapping;
 }
-- 
2.50.1