From 6e9115adb502b7d5d19b17b29fb210269f43066e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 12 Jul 2018 18:03:56 +0000 Subject: [PATCH] [X86][FastISel] Choose EVEX instructions when possible when lowering x86_sse_cvttss2si and similar intrinsics. This should fix a machine verifier error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336924 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86FastISel.cpp | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index b37b2835ac1..4199eb2ad27 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -2996,18 +2996,22 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { if (!isTypeLegal(RetTy, VT)) return false; - static const uint16_t CvtOpc[2][2][2] = { - { { X86::CVTTSS2SIrr, X86::VCVTTSS2SIrr }, - { X86::CVTTSS2SI64rr, X86::VCVTTSS2SI64rr } }, - { { X86::CVTTSD2SIrr, X86::VCVTTSD2SIrr }, - { X86::CVTTSD2SI64rr, X86::VCVTTSD2SI64rr } } + static const uint16_t CvtOpc[3][2][2] = { + { { X86::CVTTSS2SIrr, X86::CVTTSS2SI64rr }, + { X86::CVTTSD2SIrr, X86::CVTTSD2SI64rr } }, + { { X86::VCVTTSS2SIrr, X86::VCVTTSS2SI64rr }, + { X86::VCVTTSD2SIrr, X86::VCVTTSD2SI64rr } }, + { { X86::VCVTTSS2SIZrr, X86::VCVTTSS2SI64Zrr }, + { X86::VCVTTSD2SIZrr, X86::VCVTTSD2SI64Zrr } }, }; - bool HasAVX = Subtarget->hasAVX(); + unsigned AVXLevel = Subtarget->hasAVX512() ? 2 : + Subtarget->hasAVX() ? 1 : + 0; unsigned Opc; switch (VT.SimpleTy) { default: llvm_unreachable("Unexpected result type."); - case MVT::i32: Opc = CvtOpc[IsInputDouble][0][HasAVX]; break; - case MVT::i64: Opc = CvtOpc[IsInputDouble][1][HasAVX]; break; + case MVT::i32: Opc = CvtOpc[AVXLevel][IsInputDouble][0]; break; + case MVT::i64: Opc = CvtOpc[AVXLevel][IsInputDouble][1]; break; } // Check if we can fold insertelement instructions into the convert. -- 2.50.1