From 6df76a341e7e5a407a05c0c03bbff5dd77e2960e Mon Sep 17 00:00:00 2001 From: "Diogo N. Sampaio" Date: Fri, 12 Apr 2019 10:43:48 +0000 Subject: [PATCH] [Aarch64] Add v8.2-a half precision element extract intrinsics Summary: Implements the intrinsics define on the ACLE to extract half precision fp scalar elements from float16x4_t and float16x8_t vector types. a.k.a: vduph_lane_f16 vduph_laneq_f16 Reviewers: pablooliveira, olista01, LukeGeeson, DavidSpickett Reviewed By: DavidSpickett Subscribers: DavidSpickett, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D60272 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@358276 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/CGBuiltin.cpp | 8 ++++++++ test/CodeGen/aarch64-v8.2a-neon-intrinsics.c | 13 +++++++++++++ 2 files changed, 21 insertions(+) diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp index 6b7ed4e8bf..02969a1908 100644 --- a/lib/CodeGen/CGBuiltin.cpp +++ b/lib/CodeGen/CGBuiltin.cpp @@ -7847,6 +7847,14 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, : Intrinsic::aarch64_neon_sqsub; return EmitNeonCall(CGM.getIntrinsic(AccInt, Int64Ty), Ops, "vqdmlXl"); } + case NEON::BI__builtin_neon_vduph_lane_f16: { + return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)), + "vget_lane"); + } + case NEON::BI__builtin_neon_vduph_laneq_f16: { + return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)), + "vgetq_lane"); + } } llvm::VectorType *VTy = GetNeonType(this, Type); diff --git a/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c b/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c index a4bf875336..a84445b62a 100644 --- a/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c +++ b/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c @@ -1618,3 +1618,16 @@ float16x8_t test_vtrn2q_f16(float16x8_t a, float16x8_t b) { return vtrn2q_f16(a, b); } +// CHECK-LABEL: @test_vduph_laneq_f16( +// CHECK: [[V:%.*]] = extractelement <8 x half> [[V2:%.*]], i32 7 +// CHECK-NEXT: ret half [[V]] +float16_t test_vduph_laneq_f16(float16x8_t vec) { + return vduph_laneq_f16(vec, 7); +} + +// CHECK-LABEL: @test_vduph_lane_f16( +// CHECK: [[V:%.*]] = extractelement <4 x half> [[V2:%.*]], i32 3 +// CHECK-NEXT: ret half [[V]] +float16_t test_vduph_lane_f16(float16x4_t vec) { + return vduph_lane_f16(vec, 3); +} -- 2.40.0