From 6d61978fa2c07cb1311bb29f45481cf3f4dbb887 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Thu, 31 Oct 2013 22:37:08 +0000 Subject: [PATCH] [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@193817 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/clang/Basic/arm_neon.td | 12 ++++++++++++ lib/CodeGen/CGBuiltin.cpp | 14 ++++++++++++++ test/CodeGen/aarch64-neon-intrinsics.c | 24 ++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td index 8f30064752..96f9aa40ef 100644 --- a/include/clang/Basic/arm_neon.td +++ b/include/clang/Basic/arm_neon.td @@ -820,6 +820,18 @@ def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">; def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">; } +//////////////////////////////////////////////////////////////////////////////// +// Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate) +def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">; +def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">; + +//////////////////////////////////////////////////////////////////////////////// +// Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate) +def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "xsi", "Sf">; +def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "usi", "Sf">; +def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xsi", "Sd">; +def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "usi", "Sd">; + //////////////////////////////////////////////////////////////////////////////// // Scalar Reduce Pairwise Addition (Scalar and Floating Point) def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHd">; diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp index 1bed488858..8f724501d2 100644 --- a/lib/CodeGen/CGBuiltin.cpp +++ b/lib/CodeGen/CGBuiltin.cpp @@ -2331,6 +2331,20 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF, case AArch64::BI__builtin_neon_vqrshrund_n_s64: Int = Intrinsic::aarch64_neon_vsqrshrun; s = "vsqrshrun"; OverloadInt = true; break; + // Scalar Signed Fixed-point Convert To Floating-Point (Immediate) + case AArch64::BI__builtin_neon_vcvts_n_f32_s32: + Int = Intrinsic::aarch64_neon_vcvtf32_n_s32; + s = "vcvtf"; OverloadInt = false; break; + case AArch64::BI__builtin_neon_vcvtd_n_f64_s64: + Int = Intrinsic::aarch64_neon_vcvtf64_n_s64; + s = "vcvtf"; OverloadInt = false; break; + // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate) + case AArch64::BI__builtin_neon_vcvts_n_f32_u32: + Int = Intrinsic::aarch64_neon_vcvtf32_n_u32; + s = "vcvtf"; OverloadInt = false; break; + case AArch64::BI__builtin_neon_vcvtd_n_f64_u64: + Int = Intrinsic::aarch64_neon_vcvtf64_n_u64; + s = "vcvtf"; OverloadInt = false; break; } if (!Int) diff --git a/test/CodeGen/aarch64-neon-intrinsics.c b/test/CodeGen/aarch64-neon-intrinsics.c index 159918fc25..6cc6a69ad1 100644 --- a/test/CodeGen/aarch64-neon-intrinsics.c +++ b/test/CodeGen/aarch64-neon-intrinsics.c @@ -7747,3 +7747,27 @@ int32_t test_vqrshrund_n_s64(int64_t a) { // CHECK: sqrshrun {{s[0-9]+}}, {{d[0-9]+}}, #63 return (int32_t)vqrshrund_n_s64(a, 63); } + +float32_t test_vcvts_n_f32_s32(int32_t a) { +// CHECK: test_vcvts_n_f32_s32 +// CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}, #0 + return (float32_t)vcvts_n_f32_s32(a, 0); +} + +float64_t test_vcvtd_n_f64_s64(int64_t a) { +// CHECK: test_vcvtd_n_f64_s64 +// CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}, #0 + return (float64_t)vcvtd_n_f64_s64(a, 0); +} + +float32_t test_vcvts_n_f32_u32(uint32_t a) { +// CHECK: test_vcvts_n_f32_u32 +// CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}, #0 + return (float32_t)vcvts_n_f32_u32(a, 0); +} + +float64_t test_vcvtd_n_f64_u64(uint64_t a) { +// CHECK: test_vcvtd_n_f64_u64 +// CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}, #0 + return (float64_t)vcvtd_n_f64_u64(a, 0); +} -- 2.50.0