From 6b814345d13a9dc5a67ce590f8a3ee4345ac2fc9 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 12 Apr 2017 18:09:05 +0000 Subject: [PATCH] MachineScheduler: Skip acyclic latency heuristic for in-order cores The current heuristic is triggered on `InFlightCount > BufferLimit` which isn't really helpful on in-order cores where BufferLimit is zero. Note that we already get latency hiding effects for in order cores by instructions staying in the pending queue on stalls; The additional latency scheduling heuristics only have minimal effects after that while occasionally increasing register pressure too much resulting in extra spills. My motivation here is additional spills/reloads ending up in a loop in 464.h264ref / BlockMotionSearch function resulting in a 4% overal regression on an in order core. rdar://30264380 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300083 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineScheduler.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index fe7b2c8399b..41e161f71e5 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -2729,7 +2729,7 @@ void GenericScheduler::registerRoots() { errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n"; } - if (EnableCyclicPath) { + if (EnableCyclicPath && SchedModel->getMicroOpBufferSize() > 0) { Rem.CyclicCritPath = DAG->computeCyclicCriticalPath(); checkAcyclicLatency(); } -- 2.40.0