From 6b6826dc5bb4e05da0d9e7fe02d32bac15b4da29 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 18 Dec 2018 13:37:04 +0000
Subject: [PATCH] [X86][SSE] Add shift combine 'out of range' tests with UNDEFs

Shows failure to simplify out of range shift amounts to UNDEF if any element is UNDEF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349483 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/combine-shl.ll | 14 ++++++++++++++
 test/CodeGen/X86/combine-sra.ll | 13 +++++++++++++
 test/CodeGen/X86/combine-srl.ll | 13 +++++++++++++
 3 files changed, 40 insertions(+)

diff --git a/test/CodeGen/X86/combine-shl.ll b/test/CodeGen/X86/combine-shl.ll
index 8e3b03e9a4b..3cb1dd65e9c 100644
--- a/test/CodeGen/X86/combine-shl.ll
+++ b/test/CodeGen/X86/combine-shl.ll
@@ -45,6 +45,20 @@ define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) {
   ret <4 x i32> %2
 }
 
+define <4 x i32> @combine_vec_shl_outofrange3(<4 x i32> %a0) {
+; SSE-LABEL: combine_vec_shl_outofrange3:
+; SSE:       # %bb.0:
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_shl_outofrange3:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = shl <4 x i32> %a0, <i32 33, i32 34, i32 35, i32 undef>
+  ret <4 x i32> %1
+}
+
 ; fold (shl x, 0) -> x
 define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) {
 ; CHECK-LABEL: combine_vec_shl_by_zero:
diff --git a/test/CodeGen/X86/combine-sra.ll b/test/CodeGen/X86/combine-sra.ll
index 9bce1a7c3b6..f8b536ac553 100644
--- a/test/CodeGen/X86/combine-sra.ll
+++ b/test/CodeGen/X86/combine-sra.ll
@@ -50,6 +50,19 @@ define <4 x i32> @combine_vec_ashr_outofrange1(<4 x i32> %x) {
   ret <4 x i32> %1
 }
 
+define <4 x i32> @combine_vec_ashr_outofrange2(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_ashr_outofrange2:
+; SSE:       # %bb.0:
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_ashr_outofrange2:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsravd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = ashr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 undef>
+  ret <4 x i32> %1
+}
+
 ; fold (sra x, 0) -> x
 define <4 x i32> @combine_vec_ashr_by_zero(<4 x i32> %x) {
 ; CHECK-LABEL: combine_vec_ashr_by_zero:
diff --git a/test/CodeGen/X86/combine-srl.ll b/test/CodeGen/X86/combine-srl.ll
index 1cecc680c76..2dd1fa74871 100644
--- a/test/CodeGen/X86/combine-srl.ll
+++ b/test/CodeGen/X86/combine-srl.ll
@@ -35,6 +35,19 @@ define <4 x i32> @combine_vec_lshr_outofrange1(<4 x i32> %x) {
   ret <4 x i32> %1
 }
 
+define <4 x i32> @combine_vec_lshr_outofrange2(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_lshr_outofrange2:
+; SSE:       # %bb.0:
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_lshr_outofrange2:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = lshr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 undef>
+  ret <4 x i32> %1
+}
+
 ; fold (srl x, 0) -> x
 define <4 x i32> @combine_vec_lshr_by_zero(<4 x i32> %x) {
 ; CHECK-LABEL: combine_vec_lshr_by_zero:
-- 
2.50.1