From 6af8afba5aca11d301258921e97a85bf32df160d Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 5 Oct 2017 20:01:38 +0000 Subject: [PATCH] [Hexagon] Give uniform names to functions changing addressing modes, NFC The new format is changeAddrMode_xx_yy, where xx is the current mode, and yy is the new one. Old name: New name: getBaseWithImmOffset changeAddrMode_abs_io getAbsoluteForm changeAddrMode_io_abs getBaseWithRegOffset changeAddrMode_io_rr xformRegToImmOffset changeAddrMode_rr_io getBaseWithLongOffset changeAddrMode_rr_ur getRegShlForm changeAddrMode_ur_rr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315013 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/Hexagon.td | 26 +++++------ lib/Target/Hexagon/HexagonInstrInfo.cpp | 55 ++++++++++++----------- lib/Target/Hexagon/HexagonInstrInfo.h | 32 ++++++++++--- lib/Target/Hexagon/HexagonOptAddrMode.cpp | 24 +++++----- 4 files changed, 81 insertions(+), 56 deletions(-) diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index df6f3ea1f16..0c1ff9693e4 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -158,7 +158,7 @@ def getNonNVStore : InstrMapping { let ValueCols = [["false"]]; } -def getBaseWithImmOffset : InstrMapping { +def changeAddrMode_abs_io: InstrMapping { let FilterClass = "AddrModeRel"; let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", "isFloat"]; @@ -167,7 +167,7 @@ def getBaseWithImmOffset : InstrMapping { let ValueCols = [["BaseImmOffset"]]; } -def getAbsoluteForm : InstrMapping { +def changeAddrMode_io_abs: InstrMapping { let FilterClass = "AddrModeRel"; let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", "isFloat"]; @@ -176,7 +176,7 @@ def getAbsoluteForm : InstrMapping { let ValueCols = [["Absolute"]]; } -def getBaseWithRegOffset : InstrMapping { +def changeAddrMode_io_rr: InstrMapping { let FilterClass = "AddrModeRel"; let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; let ColFields = ["addrMode"]; @@ -184,7 +184,7 @@ def getBaseWithRegOffset : InstrMapping { let ValueCols = [["BaseRegOffset"]]; } -def xformRegToImmOffset : InstrMapping { +def changeAddrMode_rr_io: InstrMapping { let FilterClass = "AddrModeRel"; let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; let ColFields = ["addrMode"]; @@ -192,7 +192,7 @@ def xformRegToImmOffset : InstrMapping { let ValueCols = [["BaseImmOffset"]]; } -def getBaseWithLongOffset : InstrMapping { +def changeAddrMode_rr_ur: InstrMapping { let FilterClass = "ImmRegShl"; let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; let ColFields = ["addrMode"]; @@ -200,6 +200,14 @@ def getBaseWithLongOffset : InstrMapping { let ValueCols = [["BaseLongOffset"]]; } +def changeAddrMode_ur_rr : InstrMapping { + let FilterClass = "ImmRegShl"; + let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; + let ColFields = ["addrMode"]; + let KeyCol = ["BaseLongOffset"]; + let ValueCols = [["BaseRegOffset"]]; +} + def getRegForm : InstrMapping { let FilterClass = "ImmRegRel"; let RowFields = ["CextOpcode", "PredSense", "PNewValue"]; @@ -208,14 +216,6 @@ def getRegForm : InstrMapping { let ValueCols = [["reg"]]; } -def getRegShlForm : InstrMapping { - let FilterClass = "ImmRegShl"; - let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; - let ColFields = ["InputType"]; - let KeyCol = ["imm"]; - let ValueCols = [["reg"]]; -} - def notTakenBranchPrediction : InstrMapping { let FilterClass = "PredRel"; let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 4721fd523f3..bcd1a5089c7 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -2704,16 +2704,16 @@ bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const { case HexagonII::Absolute: // Load/store with absolute addressing mode can be converted into // base+offset mode. - NonExtOpcode = Hexagon::getBaseWithImmOffset(MI.getOpcode()); + NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode()); break; case HexagonII::BaseImmOffset: // Load/store with base+offset addressing mode can be converted into // base+register offset addressing mode. However left shift operand should // be set to 0. - NonExtOpcode = Hexagon::getBaseWithRegOffset(MI.getOpcode()); + NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode()); break; case HexagonII::BaseLongOffset: - NonExtOpcode = Hexagon::getRegShlForm(MI.getOpcode()); + NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode()); break; default: return false; @@ -2827,10 +2827,6 @@ bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef Cond) const { return !isPredicatedTrue(Cond[0].getImm()); } -short HexagonInstrInfo::getAbsoluteForm(const MachineInstr &MI) const { - return Hexagon::getAbsoluteForm(MI.getOpcode()); -} - unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const { const uint64_t F = MI.getDesc().TSFlags; return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask; @@ -2963,20 +2959,6 @@ SmallVector HexagonInstrInfo::getBranchingInstrs( return Jumpers; } -short HexagonInstrInfo::getBaseWithLongOffset(short Opcode) const { - if (Opcode < 0) - return -1; - return Hexagon::getBaseWithLongOffset(Opcode); -} - -short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr &MI) const { - return Hexagon::getBaseWithLongOffset(MI.getOpcode()); -} - -short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr &MI) const { - return Hexagon::getBaseWithRegOffset(MI.getOpcode()); -} - // Returns Operand Index for the constant extended instruction. unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const { const uint64_t F = MI.getDesc().TSFlags; @@ -3892,11 +3874,11 @@ short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const { // Check addressing mode and retrieve non-ext equivalent instruction. switch (getAddrMode(MI)) { case HexagonII::Absolute: - return Hexagon::getBaseWithImmOffset(MI.getOpcode()); + return Hexagon::changeAddrMode_abs_io(MI.getOpcode()); case HexagonII::BaseImmOffset: - return Hexagon::getBaseWithRegOffset(MI.getOpcode()); + return Hexagon::changeAddrMode_io_rr(MI.getOpcode()); case HexagonII::BaseLongOffset: - return Hexagon::getRegShlForm(MI.getOpcode()); + return Hexagon::changeAddrMode_ur_rr(MI.getOpcode()); default: return -1; @@ -4075,6 +4057,27 @@ bool HexagonInstrInfo::validateBranchCond(const ArrayRef &Cond) return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1)); } -short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr &MI) const { - return Hexagon::xformRegToImmOffset(MI.getOpcode()); +// Addressing mode relations. +short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const { + return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc; +} + +short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const { + return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc; +} + +short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const { + return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc; +} + +short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const { + return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc; +} + +short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const { + return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc; +} + +short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const { + return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc; } diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 63bdb1e5cd2..2f172340c4e 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -411,13 +411,9 @@ public: bool PredOpcodeHasJMP_c(unsigned Opcode) const; bool predOpcodeHasNot(ArrayRef Cond) const; - short getAbsoluteForm(const MachineInstr &MI) const; unsigned getAddrMode(const MachineInstr &MI) const; unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const; - short getBaseWithLongOffset(short Opcode) const; - short getBaseWithLongOffset(const MachineInstr &MI) const; - short getBaseWithRegOffset(const MachineInstr &MI) const; SmallVector getBranchingInstrs(MachineBasicBlock& MBB) const; unsigned getCExtOpNum(const MachineInstr &MI) const; HexagonII::CompoundGroup @@ -465,7 +461,33 @@ public: bool reversePredSense(MachineInstr &MI) const; unsigned reversePrediction(unsigned Opcode) const; bool validateBranchCond(const ArrayRef &Cond) const; - short xformRegToImmOffset(const MachineInstr &MI) const; + + // Addressing mode relations. + short changeAddrMode_abs_io(short Opc) const; + short changeAddrMode_io_abs(short Opc) const; + short changeAddrMode_io_rr(short Opc) const; + short changeAddrMode_rr_io(short Opc) const; + short changeAddrMode_rr_ur(short Opc) const; + short changeAddrMode_ur_rr(short Opc) const; + + short changeAddrMode_abs_io(const MachineInstr &MI) const { + return changeAddrMode_abs_io(MI.getOpcode()); + } + short changeAddrMode_io_abs(const MachineInstr &MI) const { + return changeAddrMode_io_abs(MI.getOpcode()); + } + short changeAddrMode_io_rr(const MachineInstr &MI) const { + return changeAddrMode_io_rr(MI.getOpcode()); + } + short changeAddrMode_rr_io(const MachineInstr &MI) const { + return changeAddrMode_rr_io(MI.getOpcode()); + } + short changeAddrMode_rr_ur(const MachineInstr &MI) const { + return changeAddrMode_rr_ur(MI.getOpcode()); + } + short changeAddrMode_ur_rr(const MachineInstr &MI) const { + return changeAddrMode_ur_rr(MI.getOpcode()); + } }; } // end namespace llvm diff --git a/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/lib/Target/Hexagon/HexagonOptAddrMode.cpp index 6481f97e99e..dba6cdf3276 100644 --- a/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -128,10 +128,10 @@ bool HexagonOptAddrMode::hasRepForm(MachineInstr &MI, unsigned TfrDefR) { if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset) // Tranform to Absolute plus register offset. - return (HII->getBaseWithLongOffset(MI) >= 0); + return (HII->changeAddrMode_rr_ur(MI) >= 0); else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) // Tranform to absolute addressing mode. - return (HII->getAbsoluteForm(MI) >= 0); + return (HII->changeAddrMode_io_abs(MI) >= 0); return false; } @@ -337,7 +337,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, if (ImmOpNum == 1) { if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) { - short NewOpCode = HII->getBaseWithLongOffset(*OldMI); + short NewOpCode = HII->changeAddrMode_rr_ur(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); MIB.add(OldMI->getOperand(0)); @@ -347,7 +347,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, OpStart = 4; Changed = true; } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) { - short NewOpCode = HII->getAbsoluteForm(*OldMI); + short NewOpCode = HII->changeAddrMode_io_abs(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) .add(OldMI->getOperand(0)); @@ -363,7 +363,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); DEBUG(dbgs() << "[TO]: " << MIB << "\n"); } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) { - short NewOpCode = HII->xformRegToImmOffset(*OldMI); + short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); MIB.add(OldMI->getOperand(0)); @@ -394,7 +394,7 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, MachineInstrBuilder MIB; if (ImmOpNum == 0) { if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) { - short NewOpCode = HII->getBaseWithLongOffset(*OldMI); + short NewOpCode = HII->changeAddrMode_rr_ur(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); MIB.add(OldMI->getOperand(1)); @@ -403,7 +403,7 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(OldMI->getOperand(3)); OpStart = 4; } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) { - short NewOpCode = HII->getAbsoluteForm(*OldMI); + short NewOpCode = HII->changeAddrMode_io_abs(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); const GlobalValue *GV = ImmOp.getGlobal(); @@ -416,7 +416,7 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); DEBUG(dbgs() << "[TO]: " << MIB << "\n"); } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) { - short NewOpCode = HII->xformRegToImmOffset(*OldMI); + short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); MIB.add(OldMI->getOperand(0)); @@ -436,10 +436,10 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, short HexagonOptAddrMode::getBaseWithLongOffset(const MachineInstr &MI) const { if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) { - short TempOpCode = HII->getBaseWithRegOffset(MI); - return HII->getBaseWithLongOffset(TempOpCode); - } else - return HII->getBaseWithLongOffset(MI); + short TempOpCode = HII->changeAddrMode_io_rr(MI); + return HII->changeAddrMode_rr_ur(TempOpCode); + } + return HII->changeAddrMode_rr_ur(MI); } bool HexagonOptAddrMode::changeAddAsl(NodeAddr AddAslUN, -- 2.40.0