From 699aa63fab37b2c7cb77c8919846b5c837e9d3c9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 14 Jun 2019 14:51:26 +0000 Subject: [PATCH] AMDGPU: Fold readlane intrinsics of constants I'm not 100% sure about this, since I'm worried about IR transforms that might end up introducing divergence downstream once replaced with a constant, but I haven't come up with an example yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363406 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../InstCombine/InstCombineCalls.cpp | 7 +++ .../InstCombine/AMDGPU/amdgcn-intrinsics.ll | 56 +++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/lib/Transforms/InstCombine/InstCombineCalls.cpp b/lib/Transforms/InstCombine/InstCombineCalls.cpp index f167762b602..347aeb6989a 100644 --- a/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -3776,6 +3776,13 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) { II->setOperand(0, UndefValue::get(Old->getType())); return II; } + case Intrinsic::amdgcn_readfirstlane: + case Intrinsic::amdgcn_readlane: { + // A constant value is trivially uniform. + if (Constant *C = dyn_cast(II->getArgOperand(0))) + return replaceInstUsesWith(*II, C); + break; + } case Intrinsic::stackrestore: { // If the save is right next to the restore, remove the restore. This can // happen when variable allocas are DCE'd. diff --git a/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll b/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll index 6c5c02569e5..1d54d78c57d 100644 --- a/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll +++ b/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll @@ -2431,6 +2431,62 @@ define void @kill_true() { ret void } +; -------------------------------------------------------------------- +; llvm.amdgcn.readfirstlane +; -------------------------------------------------------------------- + +declare i32 @llvm.amdgcn.readfirstlane(i32) + +@gv = constant i32 0 + +define amdgpu_kernel void @readfirstlane_constant(i32 %arg) { +; CHECK-LABEL: @readfirstlane_constant( +; CHECK-NEXT: %var = call i32 @llvm.amdgcn.readfirstlane(i32 %arg) +; CHECK-NEXT: store volatile i32 %var, i32* undef, align 4 +; CHECK-NEXT: store volatile i32 0, i32* undef, align 4 +; CHECK-NEXT: store volatile i32 123, i32* undef, align 4 +; CHECK-NEXT: store volatile i32 ptrtoint (i32* @gv to i32), i32* undef, align 4 +; CHECK-NEXT: store volatile i32 undef, i32* undef, align 4 + %var = call i32 @llvm.amdgcn.readfirstlane(i32 %arg) + %zero = call i32 @llvm.amdgcn.readfirstlane(i32 0) + %imm = call i32 @llvm.amdgcn.readfirstlane(i32 123) + %constexpr = call i32 @llvm.amdgcn.readfirstlane(i32 ptrtoint (i32* @gv to i32)) + %undef = call i32 @llvm.amdgcn.readfirstlane(i32 undef) + store volatile i32 %var, i32* undef + store volatile i32 %zero, i32* undef + store volatile i32 %imm, i32* undef + store volatile i32 %constexpr, i32* undef + store volatile i32 %undef, i32* undef + ret void +} + +; -------------------------------------------------------------------- +; llvm.amdgcn.readlane +; -------------------------------------------------------------------- + +declare i32 @llvm.amdgcn.readlane(i32, i32) + +define amdgpu_kernel void @readlane_constant(i32 %arg, i32 %lane) { +; CHECK-LABEL: @readlane_constant( +; CHECK-NEXT: %var = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 7) +; CHECK-NEXT: store volatile i32 %var, i32* undef, align 4 +; CHECK-NEXT: store volatile i32 0, i32* undef, align 4 +; CHECK-NEXT: store volatile i32 123, i32* undef, align 4 +; CHECK-NEXT: store volatile i32 ptrtoint (i32* @gv to i32), i32* undef, align 4 +; CHECK-NEXT: store volatile i32 undef, i32* undef, align 4 + %var = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 7) + %zero = call i32 @llvm.amdgcn.readlane(i32 0, i32 %lane) + %imm = call i32 @llvm.amdgcn.readlane(i32 123, i32 %lane) + %constexpr = call i32 @llvm.amdgcn.readlane(i32 ptrtoint (i32* @gv to i32), i32 %lane) + %undef = call i32 @llvm.amdgcn.readlane(i32 undef, i32 %lane) + store volatile i32 %var, i32* undef + store volatile i32 %zero, i32* undef + store volatile i32 %imm, i32* undef + store volatile i32 %constexpr, i32* undef + store volatile i32 %undef, i32* undef + ret void +} + ; -------------------------------------------------------------------- ; llvm.amdgcn.update.dpp.i32 ; -------------------------------------------------------------------- -- 2.40.0