From 66554b3e516a3c11e1857aa52b0fa9ca4e2813bb Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 6 Mar 2019 14:22:21 +0000 Subject: [PATCH] [DAGCombiner] Add SADDO/SSUBO combine support Basic constant handling folds, for both scalars and vectors Differential Revision: https://reviews.llvm.org/D58967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355506 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 54 ++++++++++++++++++++++++ test/CodeGen/X86/combine-addo.ll | 22 ---------- test/CodeGen/X86/combine-subo.ll | 37 ++-------------- test/CodeGen/X86/xaluo.ll | 6 +-- 4 files changed, 60 insertions(+), 59 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c99bb535b1d..a839073e63d 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -295,9 +295,11 @@ namespace { SDValue visitADDSAT(SDNode *N); SDValue visitSUBSAT(SDNode *N); SDValue visitADDC(SDNode *N); + SDValue visitSADDO(SDNode *N); SDValue visitUADDO(SDNode *N); SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N); SDValue visitSUBC(SDNode *N); + SDValue visitSSUBO(SDNode *N); SDValue visitUSUBO(SDNode *N); SDValue visitADDE(SDNode *N); SDValue visitADDCARRY(SDNode *N); @@ -1492,8 +1494,10 @@ SDValue DAGCombiner::visit(SDNode *N) { case ISD::SSUBSAT: case ISD::USUBSAT: return visitSUBSAT(N); case ISD::ADDC: return visitADDC(N); + case ISD::SADDO: return visitSADDO(N); case ISD::UADDO: return visitUADDO(N); case ISD::SUBC: return visitSUBC(N); + case ISD::SSUBO: return visitSSUBO(N); case ISD::USUBO: return visitUSUBO(N); case ISD::ADDE: return visitADDE(N); case ISD::ADDCARRY: return visitADDCARRY(N); @@ -2410,6 +2414,31 @@ static bool isBooleanFlip(SDValue V, EVT VT, const TargetLowering &TLI) { llvm_unreachable("Unsupported boolean content"); } +// TODO: merge this with DAGCombiner::visitUADDO +SDValue DAGCombiner::visitSADDO(SDNode *N) { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + EVT VT = N0.getValueType(); + EVT CarryVT = N->getValueType(1); + SDLoc DL(N); + + // If the flag result is dead, turn this into an ADD. + if (!N->hasAnyUseOfValue(1)) + return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), + DAG.getUNDEF(CarryVT)); + + // canonicalize constant to RHS. + if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && + !DAG.isConstantIntBuildVectorOrConstantInt(N1)) + return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N1, N0); + + // fold (saddo x, 0) -> x + no carry out + if (isNullOrNullSplat(N1)) + return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT)); + + return SDValue(); +} + SDValue DAGCombiner::visitUADDO(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); @@ -2894,6 +2923,31 @@ SDValue DAGCombiner::visitSUBC(SDNode *N) { return SDValue(); } +// TODO: merge this with DAGCombiner::visitUSUBO +SDValue DAGCombiner::visitSSUBO(SDNode *N) { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + EVT VT = N0.getValueType(); + EVT CarryVT = N->getValueType(1); + SDLoc DL(N); + + // If the flag result is dead, turn this into an SUB. + if (!N->hasAnyUseOfValue(1)) + return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1), + DAG.getUNDEF(CarryVT)); + + // fold (ssubo x, x) -> 0 + no borrow + if (N0 == N1) + return CombineTo(N, DAG.getConstant(0, DL, VT), + DAG.getConstant(0, DL, CarryVT)); + + // fold (ssubo x, 0) -> x + no borrow + if (isNullOrNullSplat(N1)) + return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT)); + + return SDValue(); +} + SDValue DAGCombiner::visitUSUBO(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); diff --git a/test/CodeGen/X86/combine-addo.ll b/test/CodeGen/X86/combine-addo.ll index 703521ad028..23e5366f5e9 100644 --- a/test/CodeGen/X86/combine-addo.ll +++ b/test/CodeGen/X86/combine-addo.ll @@ -13,15 +13,11 @@ define i32 @combine_sadd_zero(i32 %a0, i32 %a1) { ; SSE-LABEL: combine_sadd_zero: ; SSE: # %bb.0: ; SSE-NEXT: movl %edi, %eax -; SSE-NEXT: addl $0, %eax -; SSE-NEXT: cmovol %esi, %eax ; SSE-NEXT: retq ; ; AVX-LABEL: combine_sadd_zero: ; AVX: # %bb.0: ; AVX-NEXT: movl %edi, %eax -; AVX-NEXT: addl $0, %eax -; AVX-NEXT: cmovol %esi, %eax ; AVX-NEXT: retq %1 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a0, i32 zeroinitializer) %2 = extractvalue {i32, i1} %1, 0 @@ -33,28 +29,10 @@ define i32 @combine_sadd_zero(i32 %a0, i32 %a1) { define <4 x i32> @combine_vec_sadd_zero(<4 x i32> %a0, <4 x i32> %a1) { ; SSE-LABEL: combine_vec_sadd_zero: ; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: pxor %xmm0, %xmm0 -; SSE-NEXT: pcmpgtd %xmm2, %xmm0 -; SSE-NEXT: pcmpeqd %xmm3, %xmm3 -; SSE-NEXT: pxor %xmm3, %xmm0 -; SSE-NEXT: pcmpeqd %xmm0, %xmm3 -; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pandn %xmm3, %xmm0 -; SSE-NEXT: blendvps %xmm0, %xmm1, %xmm2 -; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_sadd_zero: ; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpcmpgtd %xmm0, %xmm2, %xmm2 -; AVX-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 -; AVX-NEXT: vpxor %xmm3, %xmm2, %xmm2 -; AVX-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm3 -; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpandn %xmm3, %xmm2, %xmm2 -; AVX-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = call {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer) %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0 diff --git a/test/CodeGen/X86/combine-subo.ll b/test/CodeGen/X86/combine-subo.ll index 15b01985bdb..c162515c257 100644 --- a/test/CodeGen/X86/combine-subo.ll +++ b/test/CodeGen/X86/combine-subo.ll @@ -13,15 +13,11 @@ define i32 @combine_ssub_zero(i32 %a0, i32 %a1) { ; SSE-LABEL: combine_ssub_zero: ; SSE: # %bb.0: ; SSE-NEXT: movl %edi, %eax -; SSE-NEXT: subl $0, %eax -; SSE-NEXT: cmovol %esi, %eax ; SSE-NEXT: retq ; ; AVX-LABEL: combine_ssub_zero: ; AVX: # %bb.0: ; AVX-NEXT: movl %edi, %eax -; AVX-NEXT: subl $0, %eax -; AVX-NEXT: cmovol %esi, %eax ; AVX-NEXT: retq %1 = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a0, i32 zeroinitializer) %2 = extractvalue {i32, i1} %1, 0 @@ -33,31 +29,10 @@ define i32 @combine_ssub_zero(i32 %a0, i32 %a1) { define <4 x i32> @combine_vec_ssub_zero(<4 x i32> %a0, <4 x i32> %a1) { ; SSE-LABEL: combine_vec_ssub_zero: ; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: pxor %xmm3, %xmm3 -; SSE-NEXT: pcmpgtd %xmm0, %xmm3 -; SSE-NEXT: pcmpeqd %xmm4, %xmm4 -; SSE-NEXT: pxor %xmm4, %xmm3 -; SSE-NEXT: movdqa %xmm3, %xmm0 -; SSE-NEXT: pcmpeqd %xmm4, %xmm0 -; SSE-NEXT: pcmpeqd %xmm3, %xmm3 -; SSE-NEXT: pxor %xmm4, %xmm3 -; SSE-NEXT: pandn %xmm3, %xmm0 -; SSE-NEXT: blendvps %xmm0, %xmm1, %xmm2 -; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_ssub_zero: ; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpcmpgtd %xmm0, %xmm2, %xmm2 -; AVX-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 -; AVX-NEXT: vpxor %xmm3, %xmm2, %xmm2 -; AVX-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm4 -; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpxor %xmm3, %xmm2, %xmm2 -; AVX-NEXT: vpandn %xmm2, %xmm4, %xmm2 -; AVX-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = call {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer) %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0 @@ -111,16 +86,12 @@ define <4 x i32> @combine_vec_usub_zero(<4 x i32> %a0, <4 x i32> %a1) { define i32 @combine_ssub_self(i32 %a0, i32 %a1) { ; SSE-LABEL: combine_ssub_self: ; SSE: # %bb.0: -; SSE-NEXT: movl %edi, %eax -; SSE-NEXT: subl %edi, %eax -; SSE-NEXT: cmovol %esi, %eax +; SSE-NEXT: xorl %eax, %eax ; SSE-NEXT: retq ; ; AVX-LABEL: combine_ssub_self: ; AVX: # %bb.0: -; AVX-NEXT: movl %edi, %eax -; AVX-NEXT: subl %edi, %eax -; AVX-NEXT: cmovol %esi, %eax +; AVX-NEXT: xorl %eax, %eax ; AVX-NEXT: retq %1 = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a0, i32 %a0) %2 = extractvalue {i32, i1} %1, 0 @@ -132,12 +103,12 @@ define i32 @combine_ssub_self(i32 %a0, i32 %a1) { define <4 x i32> @combine_vec_ssub_self(<4 x i32> %a0, <4 x i32> %a1) { ; SSE-LABEL: combine_vec_ssub_self: ; SSE: # %bb.0: -; SSE-NEXT: psubd %xmm0, %xmm0 +; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_ssub_self: ; AVX: # %bb.0: -; AVX-NEXT: vpsubd %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = call {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a0) %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0 diff --git a/test/CodeGen/X86/xaluo.ll b/test/CodeGen/X86/xaluo.ll index 2cb664dafb6..70d36fd7fa1 100644 --- a/test/CodeGen/X86/xaluo.ll +++ b/test/CodeGen/X86/xaluo.ll @@ -193,14 +193,12 @@ define zeroext i1 @saddoinci64(i64 %v1, i64* %res) { } ; SADDO reg, imm | imm, reg -; FIXME: DAG doesn't optimize immediates on the LHS. define zeroext i1 @saddoi64imm1(i64 %v1, i64* %res) { ; SDAG-LABEL: saddoi64imm1: ; SDAG: ## %bb.0: -; SDAG-NEXT: movl $2, %ecx -; SDAG-NEXT: addq %rdi, %rcx +; SDAG-NEXT: addq $2, %rdi ; SDAG-NEXT: seto %al -; SDAG-NEXT: movq %rcx, (%rsi) +; SDAG-NEXT: movq %rdi, (%rsi) ; SDAG-NEXT: retq ; ; FAST-LABEL: saddoi64imm1: -- 2.40.0