From 63292d1bbabaebcfe3cc7d7fe5c0314b1d275a7d Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Thu, 21 May 2015 20:48:49 +0000 Subject: [PATCH] [PPC64] Handle vpkudum mask pattern correctly when vpkudum isn't available My recent patch to add support for ISA 2.07 vector pack/unpack instructions didn't properly check for availability of the vpkudum instruction when recognizing it as a special vector shuffle case. This causes us to leave the vector shuffle in place (rather than converting it to a vector permute) so that it can be recognized later as a vpkudum, but that pattern is invalid for processors prior to POWER8. Thus LLVM crashes with an "unable to select" message. We observed this since one of our buildbots is configured to generate code for a POWER7. This patch fixes the problem by checking for availability of the vpkudum instruction during custom lowering of vector shuffles. I've added a test case variant for the vpkudum pattern when the instruction isn't available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237952 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 9 ++++++++- test/CodeGen/PowerPC/vec_shuffle_p8vector.ll | 11 +++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 171f6bf0938..43ffef2dcff 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1164,13 +1164,20 @@ bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, } /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a -/// VPKUDUM instruction. +/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the +/// current subtarget. +/// /// The ShuffleKind distinguishes between big-endian operations with /// two different inputs (0), either-endian operations with two identical /// inputs (1), and little-endian operations with two different inputs (2). /// For the latter, the input operands are swapped (see PPCInstrAltivec.td). bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) { + const PPCSubtarget& Subtarget = + static_cast(DAG.getSubtarget()); + if (!Subtarget.hasP8Vector()) + return false; + bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian(); if (ShuffleKind == 0) { if (IsLE) diff --git a/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll b/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll index d81aa729f8e..77802348d8e 100644 --- a/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll +++ b/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll @@ -1,4 +1,5 @@ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck -check-prefix=CHECK-PWR7 %s define void @VPKUDUM_unary(<2 x i64>* %A) { entry: @@ -17,7 +18,12 @@ entry: ; CHECK-LABEL: @VPKUDUM_unary ; CHECK-NOT: vperm +; CHECK-NOT: vmrglw +; CHECK-NOT: vmrghw ; CHECK: vpkudum +; CHECK-PWR7: vmrglw +; CHECK-PWR7: vmrghw +; CHECK-PWR7: vmrglw define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) { entry: @@ -40,4 +46,9 @@ entry: ; CHECK-LABEL: @VPKUDUM ; CHECK-NOT: vperm +; CHECK-NOT: vmrglw +; CHECK-NOT: vmrghw ; CHECK: vpkudum +; CHECK-PWR7: vmrglw +; CHECK-PWR7: vmrghw +; CHECK-PWR7: vmrglw -- 2.40.0