From 6167d7fb789fe72d6c40b5de2ec75213407bfaa0 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 30 Oct 2013 14:45:14 +0000 Subject: [PATCH] [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/clang/Basic/BuiltinsMips.def | 16 ++++++++-------- test/CodeGen/builtins-mips-msa.c | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/clang/Basic/BuiltinsMips.def b/include/clang/Basic/BuiltinsMips.def index 2f18ed3f84..091f77f476 100644 --- a/include/clang/Basic/BuiltinsMips.def +++ b/include/clang/Basic/BuiltinsMips.def @@ -266,20 +266,20 @@ BUILTIN(__builtin_msa_binsl_h, "V8UsV8UsV8Us", "nc") BUILTIN(__builtin_msa_binsl_w, "V4UiV4UiV4Ui", "nc") BUILTIN(__builtin_msa_binsl_d, "V2ULLiV2ULLiV2ULLi", "nc") -BUILTIN(__builtin_msa_binsli_b, "V16UcV16UcIUi", "nc") -BUILTIN(__builtin_msa_binsli_h, "V8UsV8UsIUi", "nc") -BUILTIN(__builtin_msa_binsli_w, "V4UiV4UiIUi", "nc") -BUILTIN(__builtin_msa_binsli_d, "V2ULLiV2ULLiIUi", "nc") +BUILTIN(__builtin_msa_binsli_b, "V16UcV16UcV16UcIUi", "nc") +BUILTIN(__builtin_msa_binsli_h, "V8UsV8UsV8UsIUi", "nc") +BUILTIN(__builtin_msa_binsli_w, "V4UiV4UiV4UiIUi", "nc") +BUILTIN(__builtin_msa_binsli_d, "V2ULLiV2ULLiV2ULLiIUi", "nc") BUILTIN(__builtin_msa_binsr_b, "V16UcV16UcV16Uc", "nc") BUILTIN(__builtin_msa_binsr_h, "V8UsV8UsV8Us", "nc") BUILTIN(__builtin_msa_binsr_w, "V4UiV4UiV4Ui", "nc") BUILTIN(__builtin_msa_binsr_d, "V2ULLiV2ULLiV2ULLi", "nc") -BUILTIN(__builtin_msa_binsri_b, "V16UcV16UcIUi", "nc") -BUILTIN(__builtin_msa_binsri_h, "V8UsV8UsIUi", "nc") -BUILTIN(__builtin_msa_binsri_w, "V4UiV4UiIUi", "nc") -BUILTIN(__builtin_msa_binsri_d, "V2ULLiV2ULLiIUi", "nc") +BUILTIN(__builtin_msa_binsri_b, "V16UcV16UcV16UcIUi", "nc") +BUILTIN(__builtin_msa_binsri_h, "V8UsV8UsV8UsIUi", "nc") +BUILTIN(__builtin_msa_binsri_w, "V4UiV4UiV4UiIUi", "nc") +BUILTIN(__builtin_msa_binsri_d, "V2ULLiV2ULLiV2ULLiIUi", "nc") BUILTIN(__builtin_msa_bmnz_v, "V16UcV16UcV16Uc", "nc") diff --git a/test/CodeGen/builtins-mips-msa.c b/test/CodeGen/builtins-mips-msa.c index 31ee79a5a0..47e16b790a 100644 --- a/test/CodeGen/builtins-mips-msa.c +++ b/test/CodeGen/builtins-mips-msa.c @@ -155,20 +155,20 @@ void test(void) { v4i32_r = __builtin_msa_binsl_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.binsl.w( v2i64_r = __builtin_msa_binsl_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.binsl.d( - v16i8_r = __builtin_msa_binsli_b(v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.binsli.b( - v8i16_r = __builtin_msa_binsli_h(v8i16_a, 25); // CHECK: call <8 x i16> @llvm.mips.binsli.h( - v4i32_r = __builtin_msa_binsli_w(v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.binsli.w( - v2i64_r = __builtin_msa_binsli_d(v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.binsli.d( + v16i8_r = __builtin_msa_binsli_b(v16i8_r, v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.binsli.b( + v8i16_r = __builtin_msa_binsli_h(v8i16_r, v8i16_a, 25); // CHECK: call <8 x i16> @llvm.mips.binsli.h( + v4i32_r = __builtin_msa_binsli_w(v4i32_r, v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.binsli.w( + v2i64_r = __builtin_msa_binsli_d(v2i64_r, v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.binsli.d( v16i8_r = __builtin_msa_binsr_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.binsr.b( v8i16_r = __builtin_msa_binsr_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.binsr.h( v4i32_r = __builtin_msa_binsr_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.binsr.w( v2i64_r = __builtin_msa_binsr_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.binsr.d( - v16i8_r = __builtin_msa_binsri_b(v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.binsri.b( - v8i16_r = __builtin_msa_binsri_h(v8i16_a, 25); // CHECK: call <8 x i16> @llvm.mips.binsri.h( - v4i32_r = __builtin_msa_binsri_w(v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.binsri.w( - v2i64_r = __builtin_msa_binsri_d(v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.binsri.d( + v16i8_r = __builtin_msa_binsri_b(v16i8_r, v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.binsri.b( + v8i16_r = __builtin_msa_binsri_h(v8i16_r, v8i16_a, 25); // CHECK: call <8 x i16> @llvm.mips.binsri.h( + v4i32_r = __builtin_msa_binsri_w(v4i32_r, v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.binsri.w( + v2i64_r = __builtin_msa_binsri_d(v2i64_r, v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.binsri.d( v16i8_r = __builtin_msa_bmnz_v(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.bmnz.v( v8i16_r = __builtin_msa_bmnz_v(v8i16_a, v8i16_b); // CHECK: call <16 x i8> @llvm.mips.bmnz.v( -- 2.40.0