From 61637f35c3cabfba43f6261f80f3ca056f969350 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 12 May 2015 14:18:11 +0000 Subject: [PATCH] R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg) TRI->getRegClass() takes a register class ID, not a register. We were using this incorrectly in a few places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237132 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIFixSGPRCopies.cpp | 13 ++++++++----- lib/Target/R600/SIFoldOperands.cpp | 4 ++-- lib/Target/R600/SIRegisterInfo.cpp | 1 + 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp index cd1b3acc5c8..142b1433265 100644 --- a/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/lib/Target/R600/SIFixSGPRCopies.cpp @@ -140,7 +140,7 @@ const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses( const TargetRegisterClass *RC = TargetRegisterInfo::isVirtualRegister(Reg) ? MRI.getRegClass(Reg) : - TRI->getRegClass(Reg); + TRI->getPhysRegClass(Reg); RC = TRI->getSubRegClass(RC, SubReg); for (MachineRegisterInfo::use_instr_iterator @@ -183,10 +183,13 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy, unsigned SrcReg = Copy.getOperand(1).getReg(); unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); - const TargetRegisterClass *DstRC - = TargetRegisterInfo::isVirtualRegister(DstReg) ? - MRI.getRegClass(DstReg) : - TRI->getRegClass(DstReg); + if (!TargetRegisterInfo::isVirtualRegister(DstReg)) { + // If the destination register is a physical register there isn't really + // much we can do to fix this. + return false; + } + + const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); const TargetRegisterClass *SrcRC; diff --git a/lib/Target/R600/SIFoldOperands.cpp b/lib/Target/R600/SIFoldOperands.cpp index 7ba5a6d7c38..d14e37a6461 100644 --- a/lib/Target/R600/SIFoldOperands.cpp +++ b/lib/Target/R600/SIFoldOperands.cpp @@ -216,7 +216,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { const TargetRegisterClass *UseRC = TargetRegisterInfo::isVirtualRegister(UseReg) ? MRI.getRegClass(UseReg) : - TRI.getRegClass(UseReg); + TRI.getPhysRegClass(UseReg); Imm = APInt(64, OpToFold.getImm()); @@ -240,7 +240,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { const TargetRegisterClass *DestRC = TargetRegisterInfo::isVirtualRegister(DestReg) ? MRI.getRegClass(DestReg) : - TRI.getRegClass(DestReg); + TRI.getPhysRegClass(DestReg); unsigned MovOp = TII->getMovOpcode(DestRC); if (MovOp == AMDGPU::COPY) diff --git a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp index 13a89743677..3529cd0449c 100644 --- a/lib/Target/R600/SIRegisterInfo.cpp +++ b/lib/Target/R600/SIRegisterInfo.cpp @@ -347,6 +347,7 @@ const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { assert(!TargetRegisterInfo::isVirtualRegister(Reg)); static const TargetRegisterClass *BaseClasses[] = { + &AMDGPU::M0RegRegClass, &AMDGPU::VGPR_32RegClass, &AMDGPU::SReg_32RegClass, &AMDGPU::VReg_64RegClass, -- 2.40.0