From 5aa083423c94b59ab1bd3052ae332aad9afa89b8 Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Tue, 21 May 2019 08:59:00 +0000 Subject: [PATCH] [AArch64][SVE2] Asm: add integer pairwise arithmetic instructions Summary: Patch adds support for the following instructions: ADDP, SMAXP, UMAXP, SMINP, UMINP The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361229 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64SVEInstrInfo.td | 7 +++ test/MC/AArch64/SVE2/addp-diagnostics.s | 37 ++++++++++++++ test/MC/AArch64/SVE2/addp.s | 59 +++++++++++++++++++++++ test/MC/AArch64/SVE2/smaxp-diagnostics.s | 37 ++++++++++++++ test/MC/AArch64/SVE2/smaxp.s | 59 +++++++++++++++++++++++ test/MC/AArch64/SVE2/sminp-diagnostics.s | 37 ++++++++++++++ test/MC/AArch64/SVE2/sminp.s | 59 +++++++++++++++++++++++ test/MC/AArch64/SVE2/umaxp-diagnostics.s | 37 ++++++++++++++ test/MC/AArch64/SVE2/umaxp.s | 59 +++++++++++++++++++++++ test/MC/AArch64/SVE2/uminp-diagnostics.s | 37 ++++++++++++++ test/MC/AArch64/SVE2/uminp.s | 59 +++++++++++++++++++++++ 11 files changed, 487 insertions(+) create mode 100644 test/MC/AArch64/SVE2/addp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/addp.s create mode 100644 test/MC/AArch64/SVE2/smaxp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/smaxp.s create mode 100644 test/MC/AArch64/SVE2/sminp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/sminp.s create mode 100644 test/MC/AArch64/SVE2/umaxp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/umaxp.s create mode 100644 test/MC/AArch64/SVE2/uminp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/uminp.s diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index 8fc77b2b275..a51f968056d 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1127,6 +1127,13 @@ let Predicates = [HasSVE2] in { defm SADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<0, "sadalp">; defm UADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<1, "uadalp">; + // SVE2 integer pairwise arithmetic + defm ADDP_ZPmZ : sve2_int_arith_pred<0b100011, "addp">; + defm SMAXP_ZPmZ : sve2_int_arith_pred<0b101001, "smaxp">; + defm UMAXP_ZPmZ : sve2_int_arith_pred<0b101011, "umaxp">; + defm SMINP_ZPmZ : sve2_int_arith_pred<0b101101, "sminp">; + defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp">; + // SVE2 integer multiply long defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">; defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">; diff --git a/test/MC/AArch64/SVE2/addp-diagnostics.s b/test/MC/AArch64/SVE2/addp-diagnostics.s new file mode 100644 index 00000000000..98538a1c043 --- /dev/null +++ b/test/MC/AArch64/SVE2/addp-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +addp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: addp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +addp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +addp z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: addp z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: addp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/addp.s b/test/MC/AArch64/SVE2/addp.s new file mode 100644 index 00000000000..24de93b86f4 --- /dev/null +++ b/test/MC/AArch64/SVE2/addp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +addp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: addp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x11,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 11 44 + +addp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: addp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x51,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 51 44 + +addp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: addp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x91,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 91 44 + +addp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: addp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d1 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +addp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: addp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d1 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +addp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: addp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d1 44 diff --git a/test/MC/AArch64/SVE2/smaxp-diagnostics.s b/test/MC/AArch64/SVE2/smaxp-diagnostics.s new file mode 100644 index 00000000000..93c824ed654 --- /dev/null +++ b/test/MC/AArch64/SVE2/smaxp-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +smaxp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: smaxp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +smaxp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smaxp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smaxp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smaxp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +smaxp z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smaxp z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smaxp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: smaxp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/smaxp.s b/test/MC/AArch64/SVE2/smaxp.s new file mode 100644 index 00000000000..3e466dd20ef --- /dev/null +++ b/test/MC/AArch64/SVE2/smaxp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +smaxp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: smaxp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x14,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 14 44 + +smaxp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: smaxp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x54,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 54 44 + +smaxp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: smaxp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x94,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 94 44 + +smaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d4 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +smaxp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: smaxp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d4 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +smaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d4 44 diff --git a/test/MC/AArch64/SVE2/sminp-diagnostics.s b/test/MC/AArch64/SVE2/sminp-diagnostics.s new file mode 100644 index 00000000000..3a2152ae073 --- /dev/null +++ b/test/MC/AArch64/SVE2/sminp-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sminp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sminp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sminp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sminp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sminp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sminp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +sminp z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sminp z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sminp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sminp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/sminp.s b/test/MC/AArch64/SVE2/sminp.s new file mode 100644 index 00000000000..5876571c5a2 --- /dev/null +++ b/test/MC/AArch64/SVE2/sminp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sminp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sminp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x16,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 16 44 + +sminp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sminp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x56,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 56 44 + +sminp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sminp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x96,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 96 44 + +sminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d6 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sminp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sminp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d6 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d6 44 diff --git a/test/MC/AArch64/SVE2/umaxp-diagnostics.s b/test/MC/AArch64/SVE2/umaxp-diagnostics.s new file mode 100644 index 00000000000..80f59b93b1d --- /dev/null +++ b/test/MC/AArch64/SVE2/umaxp-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +umaxp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: umaxp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +umaxp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umaxp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umaxp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umaxp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +umaxp z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umaxp z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umaxp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: umaxp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/umaxp.s b/test/MC/AArch64/SVE2/umaxp.s new file mode 100644 index 00000000000..fd8c213039f --- /dev/null +++ b/test/MC/AArch64/SVE2/umaxp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +umaxp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: umaxp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x15,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 15 44 + +umaxp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: umaxp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x55,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 55 44 + +umaxp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: umaxp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x95,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 95 44 + +umaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d5 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +umaxp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: umaxp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d5 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +umaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d5 44 diff --git a/test/MC/AArch64/SVE2/uminp-diagnostics.s b/test/MC/AArch64/SVE2/uminp-diagnostics.s new file mode 100644 index 00000000000..fe0f102c77d --- /dev/null +++ b/test/MC/AArch64/SVE2/uminp-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uminp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uminp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uminp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uminp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uminp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uminp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +uminp z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uminp z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uminp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uminp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/uminp.s b/test/MC/AArch64/SVE2/uminp.s new file mode 100644 index 00000000000..b5ce206d913 --- /dev/null +++ b/test/MC/AArch64/SVE2/uminp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uminp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uminp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x17,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 17 44 + +uminp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uminp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x57,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 57 44 + +uminp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uminp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x97,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 97 44 + +uminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d7 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uminp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uminp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d7 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d7 44 -- 2.40.0