From 5893e44c14b9b0dea6ba1d7786ab80b405dfd883 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 2 Feb 2019 17:35:06 +0000 Subject: [PATCH] [SDAG] Add SDNode/SDValue getConstantOperandAPInt helper. NFCI. We already have the getConstantOperandVal helper which returns a uint64_t, but along comes the fuzzer and inserts a i128 -1 constant or something and the whole thing asserts....... I've updated a few obvious cases, and tried to make use of the const reference where possible, but there's more to do. A number of existing oss-fuzz tickets should be fixed if we start using APInt and perform value clamping where necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352961 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGNodes.h | 12 +++++++++++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- lib/Target/X86/X86ISelLowering.cpp | 26 ++++++++++-------------- 3 files changed, 24 insertions(+), 16 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 936c3c5bd15..23d353beb09 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -183,6 +183,7 @@ public: inline unsigned getNumOperands() const; inline const SDValue &getOperand(unsigned i) const; inline uint64_t getConstantOperandVal(unsigned i) const; + inline const APInt &getConstantOperandAPInt(unsigned i) const; inline bool isTargetMemoryOpcode() const; inline bool isTargetOpcode() const; inline bool isMachineOpcode() const; @@ -904,6 +905,9 @@ public: /// Helper method returns the integer value of a ConstantSDNode operand. inline uint64_t getConstantOperandVal(unsigned Num) const; + /// Helper method returns the APInt of a ConstantSDNode operand. + inline const APInt &getConstantOperandAPInt(unsigned Num) const; + const SDValue &getOperand(unsigned Num) const { assert(Num < NumOperands && "Invalid child # of SDNode!"); return OperandList[Num]; @@ -1131,6 +1135,10 @@ inline uint64_t SDValue::getConstantOperandVal(unsigned i) const { return Node->getConstantOperandVal(i); } +inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const { + return Node->getConstantOperandAPInt(i); +} + inline bool SDValue::isTargetOpcode() const { return Node->isTargetOpcode(); } @@ -1543,6 +1551,10 @@ uint64_t SDNode::getConstantOperandVal(unsigned Num) const { return cast(getOperand(Num))->getZExtValue(); } +const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const { + return cast(getOperand(Num))->getAPIntValue(); +} + class ConstantFPSDNode : public SDNode { friend class SelectionDAG; diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f5339479b54..0d41e51f48d 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -16350,7 +16350,7 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) { return SDValue(); SDValue ExtractedFromVec = Op.getOperand(0); - APInt ExtractIdx = cast(Op.getOperand(1))->getAPIntValue(); + const APInt &ExtractIdx = Op.getConstantOperandAPInt(1); if (ExtractIdx.uge(ExtractedFromVec.getValueType().getVectorNumElements())) return SDValue(); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 00a9d7cbf1c..2fc4d2c2907 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -11778,13 +11778,11 @@ static SDValue lowerShuffleOfExtractsAsVperm(const SDLoc &DL, SDValue N0, // if the extract of the low half is N1. unsigned NumElts = VT.getVectorNumElements(); SmallVector NewMask(Mask.begin(), Mask.end()); - APInt ExtIndex0 = cast(N0.getOperand(1))->getAPIntValue(); - APInt ExtIndex1 = cast(N1.getOperand(1))->getAPIntValue(); - if (ExtIndex1 == 0 && ExtIndex0 == NumElts) { - std::swap(ExtIndex0, ExtIndex1); + const APInt &ExtIndex0 = N0.getConstantOperandAPInt(1); + const APInt &ExtIndex1 = N1.getConstantOperandAPInt(1); + if (ExtIndex1 == 0 && ExtIndex0 == NumElts) ShuffleVectorSDNode::commuteMask(NewMask); - } - if (ExtIndex0 != 0 || ExtIndex1 != NumElts) + else if (ExtIndex0 != 0 || ExtIndex1 != NumElts) return SDValue(); // Final bailout: if the mask is simple, we are better off using an extract @@ -30462,7 +30460,7 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode( case X86ISD::VSHLI: { SDValue Src = Op.getOperand(0); - APInt ShiftVal = cast(Op.getOperand(1))->getAPIntValue(); + const APInt &ShiftVal = Op.getConstantOperandAPInt(1); if (ShiftVal.uge(VTBits)) return VTBits; // Shifted all bits out --> zero. unsigned Tmp = DAG.ComputeNumSignBits(Src, DemandedElts, Depth + 1); @@ -30473,7 +30471,7 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode( case X86ISD::VSRAI: { SDValue Src = Op.getOperand(0); - APInt ShiftVal = cast(Op.getOperand(1))->getAPIntValue(); + APInt ShiftVal = Op.getConstantOperandAPInt(1); if (ShiftVal.uge(VTBits - 1)) return VTBits; // Sign splat. unsigned Tmp = DAG.ComputeNumSignBits(Src, DemandedElts, Depth + 1); @@ -34079,8 +34077,7 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG, isa(EltIdx) && isa(InputVector.getOperand(0))) { uint64_t ExtractedElt = N->getConstantOperandVal(1); - auto *InputC = cast(InputVector.getOperand(0)); - const APInt &InputValue = InputC->getAPIntValue(); + const APInt &InputValue = InputVector.getConstantOperandAPInt(0); uint64_t Res = InputValue[ExtractedElt]; return DAG.getConstant(Res, dl, MVT::i1); } @@ -35808,7 +35805,7 @@ static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG) { N1C && N0.getOpcode() == ISD::AND && N0.getOperand(1).getOpcode() == ISD::Constant) { SDValue N00 = N0.getOperand(0); - APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); + APInt Mask = N0.getConstantOperandAPInt(1); Mask <<= N1C->getAPIntValue(); bool MaskOK = false; // We can handle cases concerning bit-widening nodes containing setcc_c if @@ -40253,9 +40250,8 @@ static SDValue combineMOVMSK(SDNode *N, SelectionDAG &DAG, assert(VT== MVT::i32 && "Unexpected result type"); APInt Imm(32, 0); for (unsigned Idx = 0, e = Src.getNumOperands(); Idx < e; ++Idx) { - SDValue In = Src.getOperand(Idx); - if (!In.isUndef() && - cast(In)->getAPIntValue().isNegative()) + if (!Src.getOperand(Idx).isUndef() && + Src.getConstantOperandAPInt(Idx).isNegative()) Imm.setBit(Idx); } return DAG.getConstant(Imm, SDLoc(N), VT); @@ -41510,7 +41506,7 @@ static SDValue combineSub(SDNode *N, SelectionDAG &DAG, // X-Y -> X+~Y+1, saving one register. if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && isa(Op1.getOperand(1))) { - APInt XorC = cast(Op1.getOperand(1))->getAPIntValue(); + const APInt &XorC = Op1.getConstantOperandAPInt(1); EVT VT = Op0.getValueType(); SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT, Op1.getOperand(0), -- 2.40.0