From 5827f9803fdf0917aa9372653526fdf25a7ecd6f Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 2 May 2019 09:21:46 +0000 Subject: [PATCH] [ARM GlobalISel] Legalize extensions to < 32 bits Make it legal to extend from e.g. s1 to s8 or s16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359766 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMLegalizerInfo.cpp | 2 +- .../ARM/GlobalISel/arm-legalize-exts.mir | 140 ++++++++++++++++-- 2 files changed, 132 insertions(+), 10 deletions(-) diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp index 689a77a9d93..71971197afe 100644 --- a/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -82,7 +82,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { } getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) - .legalForCartesianProduct({s32}, {s1, s8, s16}); + .legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16}); getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) .legalFor({s32}) diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir index 672b42671a1..6fa6f58e11a 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir @@ -1,13 +1,20 @@ # RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s --- | - define void @test_zext_s16() { ret void } - define void @test_sext_s8() { ret void } - define void @test_anyext_s1() { ret void } + define void @test_zext_s16_to_s32() { ret void } + define void @test_sext_s8_to_s32() { ret void } + define void @test_anyext_s1_to_s32() { ret void } + + define void @test_zext_s8_to_s16() { ret void } + define void @test_sext_s1_to_s16() { ret void } + + define void @test_anyext_s1_to_s8() { ret void } + + define void @test_ext_combine() { ret void } ... --- -name: test_zext_s16 -# CHECK-LABEL: name: test_zext_s16 +name: test_zext_s16_to_s32 +# CHECK-LABEL: name: test_zext_s16_to_s32 legalized: false # CHECK: legalized: true regBankSelected: false @@ -30,8 +37,8 @@ body: | BX_RET 14, $noreg, implicit $r0 ... --- -name: test_sext_s8 -# CHECK-LABEL: name: test_sext_s8 +name: test_sext_s8_to_s32 +# CHECK-LABEL: name: test_sext_s8_to_s32 legalized: false # CHECK: legalized: true regBankSelected: false @@ -54,8 +61,8 @@ body: | BX_RET 14, $noreg, implicit $r0 ... --- -name: test_anyext_s1 -# CHECK-LABEL: name: test_anyext_s1 +name: test_anyext_s1_to_s32 +# CHECK-LABEL: name: test_anyext_s1_to_s32 legalized: false # CHECK: legalized: true regBankSelected: false @@ -77,3 +84,118 @@ body: | $r0 = COPY %2(s32) BX_RET 14, $noreg, implicit $r0 ... +--- +name: test_zext_s8_to_s16 +# CHECK-LABEL: name: test_zext_s8_to_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: $r0 + + %0(p0) = COPY $r0 + %1(s8) = G_LOAD %0(p0) :: (load 1) + %2(s16) = G_ZEXT %1 + ; G_ZEXT from s8 to s16 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s16) = G_ZEXT {{%[0-9]+}}(s8) + G_STORE %2(s16), %0(p0) :: (store 2) + BX_RET 14, $noreg +... +--- +name: test_sext_s1_to_s16 +# CHECK-LABEL: name: test_sext_s1_to_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: $r0 + + %0(p0) = COPY $r0 + %1(s1) = G_LOAD %0(p0) :: (load 1) + %2(s16) = G_SEXT %1(s1) + ; G_SEXT from s1 to s16 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s16) = G_SEXT {{%[0-9]+}}(s1) + G_STORE %2(s16), %0(p0) :: (store 2) + BX_RET 14, $noreg +... +--- +name: test_anyext_s1_to_s8 +# CHECK-LABEL: name: test_anyext_s1_to_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: $r0 + + %0(p0) = COPY $r0 + %1(s1) = G_LOAD %0(p0) :: (load 1) + %2(s8) = G_ANYEXT %1 + ; G_ANYEXT from s1 to s8 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s8) = G_ANYEXT {{%[0-9]+}}(s1) + G_STORE %2(s8), %0(p0) :: (store 1) + BX_RET 14, $noreg +... +--- +name: test_ext_combine +# CHECK-LABEL: name: test_ext_combine +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: $r0 + + %0(p0) = COPY $r0 + %1(s8) = G_LOAD %0(p0) :: (load 1) + ; CHECK: [[V8:%[0-9]+]]:_(s8) = G_LOAD + + %2(s16) = G_ZEXT %1 + %3(s16) = G_SEXT %1 + + %4(s16) = G_OR %2, %3 + ; G_OR is going to widen to 32 bits and the extensions/truncs should combine + ; with the already existing ones + ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[V8]](s8) + ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[V8]](s8) + ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SEXT]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[OR]] + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[BITS]](s32) + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[BITS]](s32) + ; CHECK: $r0 = COPY [[ASHR]] + + %5(s32) = G_SEXT %4(s16) + $r0 = COPY %5 + + BX_RET 14, $noreg, implicit $r0 +... -- 2.40.0