From 57e555600b5f10c95e49ff513a7aca5a0d1400ff Mon Sep 17 00:00:00 2001
From: Coby Tayree <coby.tayree@intel.com>
Date: Sun, 20 Nov 2016 17:19:55 +0000
Subject: [PATCH] The 'vpmultishiftqb' instruction was implemented falsely,
 this patch amend it. More specifically - (MS dialect) broadcasting variants
 were implemented falsely.

Differential Revision: https://reviews.llvm.org/D26257



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287501 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86InstrAVX512.td             |  4 +--
 test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s | 37 ++++++++++++++++++++
 2 files changed, 39 insertions(+), 2 deletions(-)
 create mode 100644 test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s

diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td
index 6a4bd48d119..485f1b2556a 100644
--- a/lib/Target/X86/X86InstrAVX512.td
+++ b/lib/Target/X86/X86InstrAVX512.td
@@ -3942,10 +3942,10 @@ multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
                         AVX512BIBase, EVEX_4V;
 
   defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
-                    (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
+                    (ins _Src.RC:$src1, _Brdct.ScalarMemOp:$src2),
                     OpcodeStr,
                     "${src2}"##_Brdct.BroadcastStr##", $src1",
-                     "$src1, ${src2}"##_Dst.BroadcastStr,
+                     "$src1, ${src2}"##_Brdct.BroadcastStr,
                     (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
                                  (_Brdct.VT (X86VBroadcast
                                           (_Brdct.ScalarLdFrag addr:$src2)))))),
diff --git a/test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s b/test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s
new file mode 100644
index 00000000000..f4809382e18
--- /dev/null
+++ b/test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s
@@ -0,0 +1,37 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl -mattr=+avx512vl,+avx512vbmi -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vpmultishiftqb xmm1, xmm2, qword ptr [rcx]{1to2}
+// CHECK:  encoding: [0x62,0xf2,0xed,0x18,0x83,0x09]
+          vpmultishiftqb xmm1, xmm2, qword ptr [rcx]{1to2}
+
+// CHECK:  vpmultishiftqb xmm1 {k1}, xmm2, qword ptr [rcx]{1to2}
+// CHECK:  encoding: [0x62,0xf2,0xed,0x19,0x83,0x09]
+          vpmultishiftqb xmm1 {k1}, xmm2, qword ptr [rcx]{1to2}
+
+// CHECK:  vpmultishiftqb xmm1 {k1} {z}, xmm2, qword ptr [rcx]{1to2}
+// CHECK:  encoding: [0x62,0xf2,0xed,0x99,0x83,0x09]
+          vpmultishiftqb xmm1 {k1} {z}, xmm2, qword ptr [rcx]{1to2}
+
+// CHECK:  vpmultishiftqb ymm1, ymm2, qword ptr [rcx]{1to4}
+// CHECK:  encoding: [0x62,0xf2,0xed,0x38,0x83,0x09]
+          vpmultishiftqb ymm1, ymm2, qword ptr [rcx]{1to4}
+
+// CHECK:  vpmultishiftqb ymm1 {k1}, ymm2, qword ptr [rcx]{1to4}
+// CHECK:  encoding: [0x62,0xf2,0xed,0x39,0x83,0x09]
+          vpmultishiftqb ymm1 {k1}, ymm2, qword ptr [rcx]{1to4}
+
+// CHECK:  vpmultishiftqb ymm1 {k1} {z}, ymm2, qword ptr [rcx]{1to4}
+// CHECK:  encoding: [0x62,0xf2,0xed,0xb9,0x83,0x09]
+          vpmultishiftqb ymm1 {k1} {z}, ymm2, qword ptr [rcx]{1to4}
+
+// CHECK:  vpmultishiftqb zmm1, zmm2, qword ptr [rcx]{1to8}
+// CHECK:  encoding: [0x62,0xf2,0xed,0x58,0x83,0x09]
+          vpmultishiftqb zmm1, zmm2, qword ptr [rcx]{1to8}
+
+// CHECK:  vpmultishiftqb zmm1 {k1}, zmm2, qword ptr [rcx]{1to8}
+// CHECK:  encoding: [0x62,0xf2,0xed,0x59,0x83,0x09]
+          vpmultishiftqb zmm1 {k1}, zmm2, qword ptr [rcx]{1to8}
+
+// CHECK:  vpmultishiftqb zmm1 {k1} {z}, zmm2, qword ptr [rcx]{1to8}
+// CHECK:  encoding: [0x62,0xf2,0xed,0xd9,0x83,0x09]
+          vpmultishiftqb zmm1 {k1} {z}, zmm2, qword ptr [rcx]{1to8}
-- 
2.50.1