From 56e1e614d14971c616534df900c2b3a1d645b7c5 Mon Sep 17 00:00:00 2001 From: Sjoerd Meijer Date: Mon, 11 Feb 2019 09:37:42 +0000 Subject: [PATCH] [ARM] LoadStoreOptimizer: reoder limit The whole design of generating LDMs/STMs is fragile and unreliable: it depends on rescheduling here in the LoadStoreOptimizer that isn't register pressure aware and regalloc that isn't aware of generating LDMs/STMs. This patch adds a (hidden) option to control the total number of instructions that can be re-ordered. I appreciate this looks only a tiny bit better than a hard-coded constant, but at least it allows more easy experimentation with different values for now. Ideally we calculate this reorder limit based on some heuristics, and take register pressure into account. I might be looking into that next. Differential Revision: https://reviews.llvm.org/D57954 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353678 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 7 ++++++- test/CodeGen/ARM/prera-ldst-insertpt.mir | 10 +++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index f64b00c0028..132030d0393 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -2047,6 +2047,11 @@ char ARMPreAllocLoadStoreOpt::ID = 0; INITIALIZE_PASS(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt", ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) +// Limit the number of instructions to be rescheduled. +// FIXME: tune this limit, and/or come up with some better heuristics. +static cl::opt InstReorderLimit("arm-prera-ldst-opt-reorder-limit", + cl::init(8), cl::Hidden); + bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { if (AssumeMisalignedLoadStores || skipFunction(Fn.getFunction())) return false; @@ -2222,7 +2227,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, } // Don't try to reschedule too many instructions. - if (NumMove == 8) // FIXME: Tune this limit. + if (NumMove == InstReorderLimit) break; // Found a mergable instruction; save information about it. diff --git a/test/CodeGen/ARM/prera-ldst-insertpt.mir b/test/CodeGen/ARM/prera-ldst-insertpt.mir index f05bae45f40..c5c463446ad 100644 --- a/test/CodeGen/ARM/prera-ldst-insertpt.mir +++ b/test/CodeGen/ARM/prera-ldst-insertpt.mir @@ -1,4 +1,6 @@ # RUN: llc -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s +# RUN: llc -run-pass arm-prera-ldst-opt -arm-prera-ldst-opt-reorder-limit=3 %s -o - | FileCheck %s +# RUN: llc -run-pass arm-prera-ldst-opt -arm-prera-ldst-opt-reorder-limit=2 %s -o - | FileCheck %s --check-prefix=CHECK-LIMIT --- | target triple = "thumbv7---eabi" @@ -79,12 +81,18 @@ body: | ; Make sure we move the paired stores next to each other, and ; insert them in an appropriate location. - ; CHECK: t2STRi12 {{.*}}, 0 + ; CHECK: t2STRi12 {{.*}}, 0 ; CHECK-NEXT: t2STRi12 {{.*}}, 4 ; CHECK-NEXT: t2STRi12 {{.*}}, 8 ; CHECK-NEXT: t2MUL ; CHECK-NEXT: t2MOVi32imm + ; CHECK-LIMIT-LABEL: name: b + ; CHECK-LIMIT: t2STRi12 {{.*}}, 0 + ; CHECK-LIMIT-NEXT: t2STRi12 {{.*}}, 4 + ; CHECK-LIMIT-NEXT: t2MUL + ; CHECK-LIMIT-NEXT: t2STRi12 {{.*}}, 8 + %4 : rgpr = t2MUL %1, %1, 14, $noreg %5 : rgpr = t2MOVi32imm -858993459 %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, $noreg -- 2.40.0