From 54d5fd31029aaa89c5fbfdd8740e6ac74ddcc6c4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 24 Apr 2018 03:36:08 +0000 Subject: [PATCH] [X86] Remove '#ifdef __x86_64__' around mask_set1_epi64 intrinsics. The unmasked versions already didn't have this restrction. I don't think gcc or icc limit these to 64-bit mode so we shouldn't either. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@330681 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Headers/avx512fintrin.h | 4 ---- lib/Headers/avx512vlintrin.h | 3 --- test/CodeGen/avx512f-builtins.c | 2 -- test/CodeGen/avx512vl-builtins.c | 2 -- 4 files changed, 11 deletions(-) diff --git a/lib/Headers/avx512fintrin.h b/lib/Headers/avx512fintrin.h index f5137428ba..2a3bd6be89 100644 --- a/lib/Headers/avx512fintrin.h +++ b/lib/Headers/avx512fintrin.h @@ -330,7 +330,6 @@ _mm512_set1_epi64(long long __d) return (__m512i)(__v8di){ __d, __d, __d, __d, __d, __d, __d, __d }; } -#ifdef __x86_64__ static __inline __m512i __DEFAULT_FN_ATTRS _mm512_maskz_set1_epi64(__mmask8 __M, long long __A) { @@ -338,7 +337,6 @@ _mm512_maskz_set1_epi64(__mmask8 __M, long long __A) (__v8di)_mm512_set1_epi64(__A), (__v8di)_mm512_setzero_si512()); } -#endif static __inline__ __m512 __DEFAULT_FN_ATTRS _mm512_broadcastss_ps(__m128 __A) @@ -9575,7 +9573,6 @@ _mm512_mask_set1_epi32 (__m512i __O, __mmask16 __M, int __A) (__v16si) __O); } -#ifdef __x86_64__ static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_mask_set1_epi64 (__m512i __O, __mmask8 __M, long long __A) { @@ -9583,7 +9580,6 @@ _mm512_mask_set1_epi64 (__m512i __O, __mmask8 __M, long long __A) (__v8di) _mm512_set1_epi64(__A), (__v8di) __O); } -#endif static __inline __m512i __DEFAULT_FN_ATTRS _mm512_set_epi8 (char __e63, char __e62, char __e61, char __e60, char __e59, diff --git a/lib/Headers/avx512vlintrin.h b/lib/Headers/avx512vlintrin.h index 16e44c3f1f..2581c05c5d 100644 --- a/lib/Headers/avx512vlintrin.h +++ b/lib/Headers/avx512vlintrin.h @@ -5368,7 +5368,6 @@ _mm256_maskz_set1_epi32( __mmask8 __M, int __A) } -#ifdef __x86_64__ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_mask_set1_epi64 (__m128i __O, __mmask8 __M, long long __A) { @@ -5400,8 +5399,6 @@ _mm256_maskz_set1_epi64 (__mmask8 __M, long long __A) (__v4di) _mm256_set1_epi64x(__A), (__v4di) _mm256_setzero_si256()); } - -#endif #define _mm_fixupimm_pd(A, B, C, imm) __extension__ ({ \ (__m128d)__builtin_ia32_fixupimmpd128_mask((__v2df)(__m128d)(A), \ diff --git a/test/CodeGen/avx512f-builtins.c b/test/CodeGen/avx512f-builtins.c index 5b44004382..9d225781ba 100644 --- a/test/CodeGen/avx512f-builtins.c +++ b/test/CodeGen/avx512f-builtins.c @@ -8051,7 +8051,6 @@ __m512i test_mm512_setr_epi32 (int __A, int __B, int __C, int __D, __I, __J, __K, __L,__M, __N, __O, __P); } -#ifdef __x86_64__ __m512i test_mm512_mask_set1_epi64 (__m512i __O, __mmask8 __M, long long __A) { // CHECK-LABEL: @test_mm512_mask_set1_epi64 @@ -8081,7 +8080,6 @@ __m512i test_mm512_maskz_set1_epi64 (__mmask8 __M, long long __A) // CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}} return _mm512_maskz_set1_epi64 (__M, __A); } -#endif __m512i test_mm512_set_epi64 (long long __A, long long __B, long long __C, diff --git a/test/CodeGen/avx512vl-builtins.c b/test/CodeGen/avx512vl-builtins.c index 3dab9d909f..56033fa010 100644 --- a/test/CodeGen/avx512vl-builtins.c +++ b/test/CodeGen/avx512vl-builtins.c @@ -4610,7 +4610,6 @@ __m256i test_mm256_maskz_set1_epi32(__mmask8 __M) { return _mm256_maskz_set1_epi32(__M, 5); } -#ifdef __x86_64__ __m128i test_mm_mask_set1_epi64(__m128i __O, __mmask8 __M, long long __A) { // CHECK-LABEL: @test_mm_mask_set1_epi64 // CHECK: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0 @@ -4650,7 +4649,6 @@ __m256i test_mm256_maskz_set1_epi64(__mmask8 __M, long long __A) { // CHECK: select <4 x i1> %{{.*}}, <4 x i64> %{{.*}}, <4 x i64> %{{.*}} return _mm256_maskz_set1_epi64(__M, __A); } -#endif __m128d test_mm_fixupimm_pd(__m128d __A, __m128d __B, __m128i __C) { // CHECK-LABEL: @test_mm_fixupimm_pd -- 2.40.0