From 5313649a34b3d2f12454480cb9cffda388ff30bb Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 21 Jun 2017 13:26:52 +0000 Subject: [PATCH] [X86][SSE] Dropped -mcpu from vector shuffle tests Use triple and attribute only for consistency git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305908 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/vector-interleave.ll | 12 ++++++------ test/CodeGen/X86/vector-shuffle-masked.ll | 2 +- test/CodeGen/X86/vector-shuffle-sse1.ll | 18 +++++++++++++++--- test/CodeGen/X86/vector-shuffle-v1.ll | 6 ++---- 4 files changed, 24 insertions(+), 14 deletions(-) diff --git a/test/CodeGen/X86/vector-interleave.ll b/test/CodeGen/X86/vector-interleave.ll index 1265ea10897..cadb02c6b5f 100644 --- a/test/CodeGen/X86/vector-interleave.ll +++ b/test/CodeGen/X86/vector-interleave.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 ; PR21281 define <64 x i16> @interleave8x8(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e, <8 x i16> %f, <8 x i16> %h, <8 x i16> %g) { diff --git a/test/CodeGen/X86/vector-shuffle-masked.ll b/test/CodeGen/X86/vector-shuffle-masked.ll index cedec449f6f..91d68646049 100644 --- a/test/CodeGen/X86/vector-shuffle-masked.ll +++ b/test/CodeGen/X86/vector-shuffle-masked.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx512vl,+avx512dq | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq | FileCheck %s --check-prefix=CHECK define <4 x i32> @mask_shuffle_v4i32_1234(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passthru, i8 %mask) { ; CHECK-LABEL: mask_shuffle_v4i32_1234: diff --git a/test/CodeGen/X86/vector-shuffle-sse1.ll b/test/CodeGen/X86/vector-shuffle-sse1.ll index d1e4947e2b0..dfab9c9fec0 100644 --- a/test/CodeGen/X86/vector-shuffle-sse1.ll +++ b/test/CodeGen/X86/vector-shuffle-sse1.ll @@ -1,7 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 | FileCheck %s --check-prefix=SSE1 - -target triple = "x86_64-unknown-unknown" +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=SSE1 define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_0001: @@ -11,6 +9,7 @@ define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_0020: ; SSE1: # BB#0: @@ -19,6 +18,7 @@ define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_0300: ; SSE1: # BB#0: @@ -27,6 +27,7 @@ define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_1000: ; SSE1: # BB#0: @@ -35,6 +36,7 @@ define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_2200: ; SSE1: # BB#0: @@ -43,6 +45,7 @@ define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_3330: ; SSE1: # BB#0: @@ -51,6 +54,7 @@ define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_3210: ; SSE1: # BB#0: @@ -59,6 +63,7 @@ define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_0011(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_0011: ; SSE1: # BB#0: @@ -67,6 +72,7 @@ define <4 x float> @shuffle_v4f32_0011(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_2233(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_2233: ; SSE1: # BB#0: @@ -75,6 +81,7 @@ define <4 x float> @shuffle_v4f32_2233(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_0022: ; SSE1: # BB#0: @@ -83,6 +90,7 @@ define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_1133: ; SSE1: # BB#0: @@ -91,6 +99,7 @@ define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_0145(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_0145: ; SSE1: # BB#0: @@ -99,6 +108,7 @@ define <4 x float> @shuffle_v4f32_0145(<4 x float> %a, <4 x float> %b) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_v4f32_6723(<4 x float> %a, <4 x float> %b) { ; SSE1-LABEL: shuffle_v4f32_6723: ; SSE1: # BB#0: @@ -250,6 +260,7 @@ define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) { %shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_mem_v4f32_0145(<4 x float> %a, <4 x float>* %pb) { ; SSE1-LABEL: shuffle_mem_v4f32_0145: ; SSE1: # BB#0: @@ -259,6 +270,7 @@ define <4 x float> @shuffle_mem_v4f32_0145(<4 x float> %a, <4 x float>* %pb) { %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle } + define <4 x float> @shuffle_mem_v4f32_6723(<4 x float> %a, <4 x float>* %pb) { ; SSE1-LABEL: shuffle_mem_v4f32_6723: ; SSE1: # BB#0: diff --git a/test/CodeGen/X86/vector-shuffle-v1.ll b/test/CodeGen/X86/vector-shuffle-v1.ll index 4ec6b86247d..4bcf18cc727 100644 --- a/test/CodeGen/X86/vector-shuffle-v1.ll +++ b/test/CodeGen/X86/vector-shuffle-v1.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f | FileCheck %s --check-prefix=AVX512F -; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512bw -mattr=+avx512vl -mattr=+avx512dq| FileCheck %s --check-prefix=VL_BW_DQ - -target triple = "x86_64-unknown-unknown" +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX512F +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw -mattr=+avx512vl -mattr=+avx512dq| FileCheck %s --check-prefix=VL_BW_DQ define <2 x i1> @shuf2i1_1_0(<2 x i1> %a) { ; AVX512F-LABEL: shuf2i1_1_0: -- 2.50.1