From 52361a0b83e88582483d90b09fadc971f2a5d54c Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 19 Jun 2019 14:25:27 +0000 Subject: [PATCH] [X86] Merge extract_subvector(*_EXTEND) and extract_subvector(*_EXTEND_VECTOR_INREG) handling. NFCI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363808 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 473cdbb575c..f474701cef5 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -43538,26 +43538,22 @@ static SDValue combineExtractSubvector(SDNode *N, SelectionDAG &DAG, return DAG.getNode(X86ISD::VFPEXT, SDLoc(N), VT, InVec.getOperand(0)); } } - if ((InOpcode == ISD::ANY_EXTEND || InOpcode == ISD::ZERO_EXTEND || - InOpcode == ISD::SIGN_EXTEND) && + if ((InOpcode == ISD::ANY_EXTEND || + InOpcode == ISD::ANY_EXTEND_VECTOR_INREG || + InOpcode == ISD::ZERO_EXTEND || + InOpcode == ISD::ZERO_EXTEND_VECTOR_INREG || + InOpcode == ISD::SIGN_EXTEND || + InOpcode == ISD::SIGN_EXTEND_VECTOR_INREG) && VT.is128BitVector() && InVec.getOperand(0).getSimpleValueType().is128BitVector()) { - unsigned ExtOp; - switch(InOpcode) { - default: llvm_unreachable("Unknown extension opcode"); + unsigned ExtOp = InOpcode; + switch (InOpcode) { case ISD::ANY_EXTEND: ExtOp = ISD::ANY_EXTEND_VECTOR_INREG; break; case ISD::SIGN_EXTEND: ExtOp = ISD::SIGN_EXTEND_VECTOR_INREG; break; case ISD::ZERO_EXTEND: ExtOp = ISD::ZERO_EXTEND_VECTOR_INREG; break; } return DAG.getNode(ExtOp, SDLoc(N), VT, InVec.getOperand(0)); } - if ((InOpcode == ISD::ANY_EXTEND_VECTOR_INREG || - InOpcode == ISD::ZERO_EXTEND_VECTOR_INREG || - InOpcode == ISD::SIGN_EXTEND_VECTOR_INREG) && - VT.is128BitVector() && - InVec.getOperand(0).getSimpleValueType().is128BitVector()) { - return DAG.getNode(InOpcode, SDLoc(N), VT, InVec.getOperand(0)); - } } return SDValue(); -- 2.40.0