From 5114e12df040b5871d66907e3fb0254190aa6ba4 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 3 Feb 2015 16:24:05 +0000 Subject: [PATCH] Revise too-restrictive test CodeGen/PowerPC/tls-pic.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227977 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/tls-pic.ll | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/test/CodeGen/PowerPC/tls-pic.ll b/test/CodeGen/PowerPC/tls-pic.ll index 9ba372591e6..2a5babef09a 100644 --- a/test/CodeGen/PowerPC/tls-pic.ll +++ b/test/CodeGen/PowerPC/tls-pic.ll @@ -19,32 +19,32 @@ entry: ; OPT0-LABEL: main: ; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha -; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l +; OPT0: addi 3, [[REG]], a@got@tlsld@l ; OPT0: bl __tls_get_addr(a@tlsld) ; OPT0-NEXT: nop ; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha -; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l +; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l ; OPT0-32-LABEL: main ; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld ; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha -; OPT0-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l +; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l ; OPT1-32-LABEL: main ; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld ; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha -; OPT1-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l +; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l ; Test peephole optimization for thread-local storage using the ; local dynamic model. ; OPT1-LABEL: main: ; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha -; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l +; OPT1: addi 3, [[REG]], a@got@tlsld@l ; OPT1: bl __tls_get_addr(a@tlsld) ; OPT1-NEXT: nop ; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha -; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) +; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) ; Test correct assembly code generation for thread-local storage using ; the general dynamic model. -- 2.40.0