From 4eed9afb35642bb9e61905c981e70aa90947af74 Mon Sep 17 00:00:00 2001 From: Eugene Leviant Date: Fri, 20 Oct 2017 14:29:17 +0000 Subject: [PATCH] [ARM] Use post-RA MI scheduler when +use-misched is set Differential revision: https://reviews.llvm.org/D39100 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316214 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMTargetMachine.cpp | 9 ++++++++- test/CodeGen/ARM/cortex-a57-misched-alu.ll | 3 +++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 9a191e42247..39b8df401aa 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -310,7 +310,14 @@ namespace { class ARMPassConfig : public TargetPassConfig { public: ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) {} + : TargetPassConfig(TM, PM) { + if (TM.getOptLevel() != CodeGenOpt::None) { + ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(), + TM.getTargetFeatureString()); + if (STI.hasFeature(ARM::FeatureUseMISched)) + substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); + } + } ARMBaseTargetMachine &getARMTargetMachine() const { return getTM(); diff --git a/test/CodeGen/ARM/cortex-a57-misched-alu.ll b/test/CodeGen/ARM/cortex-a57-misched-alu.ll index 960ee87532b..2ced60fbf0d 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-alu.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-alu.ll @@ -1,5 +1,6 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED ; Check the latency for ALU shifted operand variants. ; @@ -60,6 +61,8 @@ ; CHECK: Ready ; CHECK-NEXT: A57UnitI +; Check that post RA MI scheduler is invoked with +use-misched +; POST-MISCHED: Before post-MI-sched target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv8r-arm-none-eabi" -- 2.40.0