From 4bbcd0ad601459e28a34d8357e2ce5e8efa38522 Mon Sep 17 00:00:00 2001 From: Sean Fertile Date: Mon, 14 Nov 2016 14:42:37 +0000 Subject: [PATCH] [PPC] add intrinsics for vec extract exp/significand and vec test data class. Differential Revision: https://reviews.llvm.org/D26272 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286829 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsPowerPC.td | 18 +++++++ lib/Target/PowerPC/PPCInstrVSX.td | 24 +++++++--- test/CodeGen/PowerPC/vsx-p9.ll | 71 ++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+), 6 deletions(-) diff --git a/include/llvm/IR/IntrinsicsPowerPC.td b/include/llvm/IR/IntrinsicsPowerPC.td index f002f0ef8a0..dc8a5f6b8ba 100644 --- a/include/llvm/IR/IntrinsicsPowerPC.td +++ b/include/llvm/IR/IntrinsicsPowerPC.td @@ -849,6 +849,24 @@ def int_ppc_vsx_xvcvdpsp : def int_ppc_vsx_xvcvsphp : PowerPC_VSX_Intrinsic<"xvcvsphp", [llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; +def int_ppc_vsx_xvxexpdp : + PowerPC_VSX_Intrinsic<"xvxexpdp", [llvm_v2i64_ty], + [llvm_v2f64_ty], [IntrNoMem]>; +def int_ppc_vsx_xvxexpsp : + PowerPC_VSX_Intrinsic<"xvxexpsp", [llvm_v4i32_ty], + [llvm_v4f32_ty], [IntrNoMem]>; +def int_ppc_vsx_xvxsigdp : + PowerPC_VSX_Intrinsic<"xvxsigdp", [llvm_v2i64_ty], + [llvm_v2f64_ty], [IntrNoMem]>; +def int_ppc_vsx_xvxsigsp : + PowerPC_VSX_Intrinsic<"xvxsigsp", [llvm_v4i32_ty], + [llvm_v4f32_ty], [IntrNoMem]>; +def int_ppc_vsx_xvtstdcdp : + PowerPC_VSX_Intrinsic<"xvtstdcdp", [llvm_v2i64_ty], + [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>; +def int_ppc_vsx_xvtstdcsp : + PowerPC_VSX_Intrinsic<"xvtstdcsp", [llvm_v4i32_ty], + [llvm_v4f32_ty,llvm_i32_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td index e9a06f3a381..cdf6a24b725 100644 --- a/lib/Target/PowerPC/PPCInstrVSX.td +++ b/lib/Target/PowerPC/PPCInstrVSX.td @@ -2206,10 +2206,18 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>; // Vector Extract Exponent/Significand DP/SP - def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, []>; - def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, []>; - def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, []>; - def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, []>; + def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, + [(set v2i64: $XT, + (int_ppc_vsx_xvxexpdp v2f64:$XB))]>; + def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, + [(set v4i32: $XT, + (int_ppc_vsx_xvxexpsp v4f32:$XB))]>; + def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, + [(set v2i64: $XT, + (int_ppc_vsx_xvxsigdp v2f64:$XB))]>; + def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, + [(set v4i32: $XT, + (int_ppc_vsx_xvxsigsp v4f32:$XB))]>; //===--------------------------------------------------------------------===// @@ -2230,10 +2238,14 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { let UseVSXReg = 1 in { def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5, (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), - "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, []>; + "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, + [(set v4i32: $XT, + (int_ppc_vsx_xvtstdcsp v4f32:$XB, imm:$DCMX))]>; def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5, (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), - "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, []>; + "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, + [(set v2i64: $XT, + (int_ppc_vsx_xvtstdcdp v2f64:$XB, imm:$DCMX))]>; } // UseVSXReg = 1 //===--------------------------------------------------------------------===// diff --git a/test/CodeGen/PowerPC/vsx-p9.ll b/test/CodeGen/PowerPC/vsx-p9.ll index 9d546ec6b15..307859c7030 100644 --- a/test/CodeGen/PowerPC/vsx-p9.ll +++ b/test/CodeGen/PowerPC/vsx-p9.ll @@ -260,4 +260,75 @@ declare <4 x i32> @llvm.ppc.altivec.vrlwnm(<4 x i32>, <4 x i32>) ; Function Attrs: nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vrldnm(<2 x i64>, <2 x i64>) +define <4 x i32> @testXVXEXPSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float> %a) + ret <4 x i32> %0 +; CHECK-LABEL: testXVXEXPSP +; CHECK: xvxexpsp 34, 34 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float>) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVXEXPDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a) + ret <2 x i64> %0 +; CHECK-LABEL: testXVXEXPDP +; CHECK xvxexpdp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>) + +; Function Attrs: nounwind readnone +define <4 x i32> @testXVXSIGSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a) + ret <4 x i32> %0 +; CHECK-LABEL: testXVXSIGSP +; CHECK xvxsigsp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVXSIGDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a) + ret <2 x i64> %0 +; CHECK-LABEL: testXVXSIGDP +; CHECK xvxsigdp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>) + +; Function Attrs: nounwind readnone +define <4 x i32> @testXVTSTDCSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 127) + ret <4 x i32> %0 +; CHECK-LABEL: testXVTSTDCSP +; CHECK: xvtstdcsp 34, 34, 127 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 %b) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVTSTDCDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 127) + ret <2 x i64> %0 +; CHECK-LABEL: testXVTSTDCDP +; CHECK: xvtstdcdp 34, 34, 127 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 %b) + declare void @sink(...) -- 2.50.1