From 4b7476c2941b3fc54a54020ec60387a24d2135f6 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Fri, 2 Dec 2016 18:21:53 +0000 Subject: [PATCH] [SystemZ] Support floating-point control register instructions Add assembler support for instructions manipulating the FPC. Also add codegen support via the GCC compatibility builtins: __builtin_s390_sfpc __builtin_s390_efpc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288525 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsSystemZ.td | 5 + lib/Target/SystemZ/SystemZInstrFP.td | 20 +++ lib/Target/SystemZ/SystemZInstrFormats.td | 32 ++++- lib/Target/SystemZ/SystemZInstrInfo.td | 12 +- lib/Target/SystemZ/SystemZOperators.td | 6 + lib/Target/SystemZ/SystemZScheduleZ13.td | 11 ++ lib/Target/SystemZ/SystemZScheduleZ196.td | 12 ++ lib/Target/SystemZ/SystemZScheduleZEC12.td | 12 ++ test/CodeGen/SystemZ/fpc-intrinsics.ll | 67 ++++++++++ test/MC/Disassembler/SystemZ/insns.txt | 135 +++++++++++++++++++++ test/MC/SystemZ/insn-bad-z196.s | 11 ++ test/MC/SystemZ/insn-bad.s | 60 +++++++++ test/MC/SystemZ/insn-good-z196.s | 14 +++ test/MC/SystemZ/insn-good.s | 94 ++++++++++++++ 14 files changed, 480 insertions(+), 11 deletions(-) create mode 100644 test/CodeGen/SystemZ/fpc-intrinsics.ll diff --git a/include/llvm/IR/IntrinsicsSystemZ.td b/include/llvm/IR/IntrinsicsSystemZ.td index bfc15b9bc09..9be37d3645b 100644 --- a/include/llvm/IR/IntrinsicsSystemZ.td +++ b/include/llvm/IR/IntrinsicsSystemZ.td @@ -382,6 +382,11 @@ let TargetPrefix = "s390" in { //===----------------------------------------------------------------------===// let TargetPrefix = "s390" in { + def int_s390_sfpc : GCCBuiltin<"__builtin_s390_sfpc">, + Intrinsic<[], [llvm_i32_ty], []>; + def int_s390_efpc : GCCBuiltin<"__builtin_s390_efpc">, + Intrinsic<[llvm_i32_ty], [], []>; + def int_s390_tdc : Intrinsic<[llvm_i32_ty], [llvm_anyfloat_ty, llvm_i64_ty], [IntrNoMem]>; } diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td index 6ef7c9c9564..bb6d27e2482 100644 --- a/lib/Target/SystemZ/SystemZInstrFP.td +++ b/lib/Target/SystemZ/SystemZInstrFP.td @@ -478,6 +478,26 @@ let Defs = [CC], CCValues = 0xC in { def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>; } +//===----------------------------------------------------------------------===// +// Floating-point control register instructions +//===----------------------------------------------------------------------===// + +let hasSideEffects = 1 in { + def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>; + def STFPC : StoreInherentS<"stfpc", 0xB29C, storei, 4>; + + def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>; + def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu, 4>; + + def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>; + def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>; + + def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>, + Requires<[FeatureFPExtension]>; + def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>; + def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>; +} + //===----------------------------------------------------------------------===// // Peepholes //===----------------------------------------------------------------------===// diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index c72879a1339..17dcd3b37bf 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -1598,6 +1598,9 @@ class ICV // LoadAddress: // One register output operand and one address operand. // +// SideEffectAddress: +// One address operand. No output operands, but causes some side effect. +// // Unary: // One register output operand and one input operand. // @@ -1677,10 +1680,12 @@ class InherentVRIa opcode, bits<16> value> let M3 = 0; } -class StoreInherentS opcode> +class StoreInherentS opcode, + SDPatternOperator operator, bits<5> bytes> : InstS { + mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> { let mayStore = 1; + let AccessBytes = bytes; } class SideEffectInherentEopcode> @@ -2265,10 +2270,27 @@ class SideEffectUnaryRRopcode, RegisterOperand cls> let R2 = 0; } +class SideEffectUnaryRRE opcode, RegisterOperand cls, + SDPatternOperator operator> + : InstRRE { + let R2 = 0; +} + class SideEffectUnaryS opcode, - SDPatternOperator operator> - : InstS; + SDPatternOperator operator, bits<5> bytes, + AddressingMode mode = bdaddr12only> + : InstS { + let mayLoad = 1; + let AccessBytes = bytes; +} + +class SideEffectAddressS opcode, + SDPatternOperator operator, + AddressingMode mode = bdaddr12only> + : InstS; class LoadAddressRX opcode, SDPatternOperator operator, AddressingMode mode> diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 57a620bca78..a7fef3ae13a 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1632,7 +1632,7 @@ let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { // Transaction Abort let isTerminator = 1, isBarrier = 1 in - def TABORT : SideEffectUnaryS<"tabort", 0xB2FC, int_s390_tabort>; + def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; // Nontransactional Store def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; @@ -1691,14 +1691,14 @@ let hasSideEffects = 1, isCall = 1, Defs = [CC] in // Store clock. let hasSideEffects = 1, Defs = [CC] in { - def STCK : StoreInherentS<"stck", 0xB205>; - def STCKF : StoreInherentS<"stckf", 0xB27C>; - def STCKE : StoreInherentS<"stcke", 0xB278>; + def STCK : StoreInherentS<"stck", 0xB205, null_frag, 8>; + def STCKF : StoreInherentS<"stckf", 0xB27C, null_frag, 8>; + def STCKE : StoreInherentS<"stcke", 0xB278, null_frag, 16>; } // Store facility list. -let hasSideEffects = 1, Defs = [CC] in - def STFLE : StoreInherentS<"stfle", 0xB2B0>; +let hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in + def STFLE : StoreInherentS<"stfle", 0xB2B0, null_frag, 0>; // Extract CPU time. let Defs = [R0D, R1D], hasSideEffects = 1, mayLoad = 1 in diff --git a/lib/Target/SystemZ/SystemZOperators.td b/lib/Target/SystemZ/SystemZOperators.td index 843ad34e7d4..fde26ed4e1c 100644 --- a/lib/Target/SystemZ/SystemZOperators.td +++ b/lib/Target/SystemZ/SystemZOperators.td @@ -570,6 +570,12 @@ class storeu : PatFrag<(ops node:$value, node:$addr), (store (operator node:$value), node:$addr)>; +// Create a store operator that performs the given inherent operation +// and stores the resulting value. +class storei + : PatFrag<(ops node:$addr), + (store (operator), node:$addr)>; + // Vector representation of all-zeros and all-ones. def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>; def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>; diff --git a/lib/Target/SystemZ/SystemZScheduleZ13.td b/lib/Target/SystemZ/SystemZScheduleZ13.td index ae6885f0913..3014a6ce494 100644 --- a/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -802,6 +802,17 @@ def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "CXBR$")>; def : InstRW<[LSU, VecXsPm, Lat9], (instregex "TC(E|D)B$")>; def : InstRW<[LSU, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "TCXB$")>; +//===----------------------------------------------------------------------===// +// FP: Floating-point control register instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat4, GroupAlone], (instregex "EFPC$")>; +def : InstRW<[FXb, LSU, Lat5, GroupAlone], (instregex "STFPC$")>; +def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>; +def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>; +def : InstRW<[FXa, Lat30, GroupAlone], (instregex "SFASR$")>; +def : InstRW<[FXa, LSU, Lat30, GroupAlone], (instregex "LFAS$")>; +def : InstRW<[FXb, Lat3, GroupAlone], (instregex "SRNM(B|T)?$")>; // --------------------------------- Vector --------------------------------- // diff --git a/lib/Target/SystemZ/SystemZScheduleZ196.td b/lib/Target/SystemZ/SystemZScheduleZ196.td index f8e0ccbcea0..67e0f2c8a2f 100644 --- a/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -731,5 +731,17 @@ def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>; def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>; def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>; +//===----------------------------------------------------------------------===// +// FP: Floating-point control register instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>; +def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>; +def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>; +def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>; +def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>; +def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>; +def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>; + } diff --git a/lib/Target/SystemZ/SystemZScheduleZEC12.td b/lib/Target/SystemZ/SystemZScheduleZEC12.td index 38d4402a74b..c1185cdd633 100644 --- a/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -769,5 +769,17 @@ def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>; def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>; def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>; +//===----------------------------------------------------------------------===// +// FP: Floating-point control register instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>; +def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>; +def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>; +def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>; +def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>; +def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>; +def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>; + } diff --git a/test/CodeGen/SystemZ/fpc-intrinsics.ll b/test/CodeGen/SystemZ/fpc-intrinsics.ll new file mode 100644 index 00000000000..fd8064b18fc --- /dev/null +++ b/test/CodeGen/SystemZ/fpc-intrinsics.ll @@ -0,0 +1,67 @@ +; Test floating-point control register intrinsics. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare void @llvm.s390.sfpc(i32) +declare i32 @llvm.s390.efpc() + +; SFPC. +define void @test_sfpc(i32 %fpc) { +; CHECK-LABEL: test_sfpc: +; CHECK: sfpc %r2 +; CHECK: br %r14 + call void @llvm.s390.sfpc(i32 %fpc) + ret void +} + +; EFPC. +define i32 @test_efpc() { +; CHECK-LABEL: test_efpc: +; CHECK: efpc %r2 +; CHECK: br %r14 + %res = call i32 @llvm.s390.efpc() + ret i32 %res +} + +; LFPC. +define void @test_lfpc1(i32 *%ptr) { +; CHECK-LABEL: test_lfpc1: +; CHECK: lfpc 0(%r2) +; CHECK: br %r14 + %fpc = load i32, i32 *%ptr + call void @llvm.s390.sfpc(i32 %fpc) + ret void +} + +; LFPC with offset. +define void @test_lfpc2(i32 *%ptr) { +; CHECK-LABEL: test_lfpc2: +; CHECK: lfpc 4092(%r2) +; CHECK: br %r14 + %ptr1 = getelementptr i32, i32 *%ptr, i32 1023 + %fpc = load i32, i32 *%ptr1 + call void @llvm.s390.sfpc(i32 %fpc) + ret void +} + +; STFPC. +define void @test_stfpc1(i32 *%ptr) { +; CHECK-LABEL: test_stfpc1: +; CHECK: stfpc 0(%r2) +; CHECK: br %r14 + %fpc = call i32 @llvm.s390.efpc() + store i32 %fpc, i32 *%ptr + ret void +} + +; STFPC with offset. +define void @test_stfpc2(i32 *%ptr) { +; CHECK-LABEL: test_stfpc2: +; CHECK: stfpc 4092(%r2) +; CHECK: br %r14 + %fpc = call i32 @llvm.s390.efpc() + %ptr1 = getelementptr i32, i32 *%ptr, i32 1023 + store i32 %fpc, i32 *%ptr1 + ret void +} + diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index c6295acf430..9d6e5dc227c 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -3898,6 +3898,15 @@ # CHECK: ectg 4095(%r1), 0(%r15), %r2 0xc8 0x21 0x1f 0xff 0xf0 0x00 +# CHECK: efpc %r0 +0xb3 0x8c 0x00 0x00 + +# CHECK: efpc %r1 +0xb3 0x8c 0x00 0x10 + +# CHECK: efpc %r15 +0xb3 0x8c 0x00 0xf0 + # CHECK: etnd %r0 0xb2 0xec 0x00 0x00 @@ -5218,6 +5227,42 @@ # CHECK: lfhat %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0xc8 +# CHECK: lfas 0 +0xb2 0xbd 0x00 0x00 + +# CHECK: lfas 0(%r1) +0xb2 0xbd 0x10 0x00 + +# CHECK: lfas 0(%r15) +0xb2 0xbd 0xf0 0x00 + +# CHECK: lfas 4095 +0xb2 0xbd 0x0f 0xff + +# CHECK: lfas 4095(%r1) +0xb2 0xbd 0x1f 0xff + +# CHECK: lfas 4095(%r15) +0xb2 0xbd 0xff 0xff + +# CHECK: lfpc 0 +0xb2 0x9d 0x00 0x00 + +# CHECK: lfpc 0(%r1) +0xb2 0x9d 0x10 0x00 + +# CHECK: lfpc 0(%r15) +0xb2 0x9d 0xf0 0x00 + +# CHECK: lfpc 4095 +0xb2 0x9d 0x0f 0xff + +# CHECK: lfpc 4095(%r1) +0xb2 0x9d 0x1f 0xff + +# CHECK: lfpc 4095(%r15) +0xb2 0x9d 0xff 0xff + # CHECK: lgbr %r0, %r15 0xb9 0x06 0x00 0x0f @@ -8689,6 +8734,24 @@ # CHECK: seb %f15, 0 0xed 0xf0 0x00 0x00 0x00 0x0b +# CHECK: sfasr %r0 +0xb3 0x85 0x00 0x00 + +# CHECK: sfasr %r1 +0xb3 0x85 0x00 0x10 + +# CHECK: sfasr %r15 +0xb3 0x85 0x00 0xf0 + +# CHECK: sfpc %r0 +0xb3 0x84 0x00 0x00 + +# CHECK: sfpc %r1 +0xb3 0x84 0x00 0x10 + +# CHECK: sfpc %r15 +0xb3 0x84 0x00 0xf0 + # CHECK: sgfr %r0, %r0 0xb9 0x19 0x00 0x00 @@ -9544,6 +9607,60 @@ # CHECK: srk %r2, %r3, %r4 0xb9 0xf9 0x40 0x23 +# CHECK: srnm 0 +0xb2 0x99 0x00 0x00 + +# CHECK: srnm 0(%r1) +0xb2 0x99 0x10 0x00 + +# CHECK: srnm 0(%r15) +0xb2 0x99 0xf0 0x00 + +# CHECK: srnm 4095 +0xb2 0x99 0x0f 0xff + +# CHECK: srnm 4095(%r1) +0xb2 0x99 0x1f 0xff + +# CHECK: srnm 4095(%r15) +0xb2 0x99 0xff 0xff + +# CHECK: srnmb 0 +0xb2 0xb8 0x00 0x00 + +# CHECK: srnmb 0(%r1) +0xb2 0xb8 0x10 0x00 + +# CHECK: srnmb 0(%r15) +0xb2 0xb8 0xf0 0x00 + +# CHECK: srnmb 4095 +0xb2 0xb8 0x0f 0xff + +# CHECK: srnmb 4095(%r1) +0xb2 0xb8 0x1f 0xff + +# CHECK: srnmb 4095(%r15) +0xb2 0xb8 0xff 0xff + +# CHECK: srnmt 0 +0xb2 0xb9 0x00 0x00 + +# CHECK: srnmt 0(%r1) +0xb2 0xb9 0x10 0x00 + +# CHECK: srnmt 0(%r15) +0xb2 0xb9 0xf0 0x00 + +# CHECK: srnmt 4095 +0xb2 0xb9 0x0f 0xff + +# CHECK: srnmt 4095(%r1) +0xb2 0xb9 0x1f 0xff + +# CHECK: srnmt 4095(%r15) +0xb2 0xb9 0xff 0xff + # CHECK: srst %r0, %r0 0xb2 0x5e 0x00 0x00 @@ -9880,6 +9997,24 @@ # CHECK: stey %f15, 0 0xed 0xf0 0x00 0x00 0x00 0x66 +# CHECK: stfpc 0 +0xb2 0x9c 0x00 0x00 + +# CHECK: stfpc 0(%r1) +0xb2 0x9c 0x10 0x00 + +# CHECK: stfpc 0(%r15) +0xb2 0x9c 0xf0 0x00 + +# CHECK: stfpc 4095 +0xb2 0x9c 0x0f 0xff + +# CHECK: stfpc 4095(%r1) +0xb2 0x9c 0x1f 0xff + +# CHECK: stfpc 4095(%r15) +0xb2 0x9c 0xff 0xff + # CHECK: stg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x24 diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s index 31d0ec56e2a..4134c05d835 100644 --- a/test/MC/SystemZ/insn-bad-z196.s +++ b/test/MC/SystemZ/insn-bad-z196.s @@ -873,6 +873,17 @@ srlk %r0,%r0,0(%r0) srlk %r0,%r0,0(%r1,%r2) +#CHECK: error: invalid operand +#CHECK: srnmb -1 +#CHECK: error: invalid operand +#CHECK: srnmb 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: srnmb 0(%r1,%r2) + + srnmb -1 + srnmb 4096 + srnmb 0(%r1,%r2) + #CHECK: error: invalid operand #CHECK: stch %r0, -524289 #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s index b2e31bd1a13..242a7431161 100644 --- a/test/MC/SystemZ/insn-bad.s +++ b/test/MC/SystemZ/insn-bad.s @@ -2007,6 +2007,28 @@ lfh %r0, 0 +#CHECK: error: invalid operand +#CHECK: lfas -1 +#CHECK: error: invalid operand +#CHECK: lfas 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lfas 0(%r1,%r2) + + lfas -1 + lfas 4096 + lfas 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: lfpc -1 +#CHECK: error: invalid operand +#CHECK: lfpc 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lfpc 0(%r1,%r2) + + lfpc -1 + lfpc 4096 + lfpc 0(%r1,%r2) + #CHECK: error: invalid operand #CHECK: lg %r0, -524289 #CHECK: error: invalid operand @@ -3537,6 +3559,33 @@ srlk %r2,%r3,4(%r5) +#CHECK: error: invalid operand +#CHECK: srnm -1 +#CHECK: error: invalid operand +#CHECK: srnm 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: srnm 0(%r1,%r2) + + srnm -1 + srnm 4096 + srnm 0(%r1,%r2) + +#CHECK: error: instruction requires: fp-extension +#CHECK: srnmb 0(%r1) + + srnmb 0(%r1) + +#CHECK: error: invalid operand +#CHECK: srnmt -1 +#CHECK: error: invalid operand +#CHECK: srnmt 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: srnmt 0(%r1,%r2) + + srnmt -1 + srnmt 4096 + srnmt 0(%r1,%r2) + #CHECK: error: invalid operand #CHECK: st %r0, -1 #CHECK: error: invalid operand @@ -3617,6 +3666,17 @@ stey %f0, -524289 stey %f0, 524288 +#CHECK: error: invalid operand +#CHECK: stfpc -1 +#CHECK: error: invalid operand +#CHECK: stfpc 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stfpc 0(%r1,%r2) + + stfpc -1 + stfpc 4096 + stfpc 0(%r1,%r2) + #CHECK: error: invalid operand #CHECK: stg %r0, -524289 #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s index 318ac2b5b2a..0dcbf7af2f6 100644 --- a/test/MC/SystemZ/insn-good-z196.s +++ b/test/MC/SystemZ/insn-good-z196.s @@ -1469,6 +1469,20 @@ srlk %r0,%r0,524287(%r1) srlk %r0,%r0,524287(%r15) +#CHECK: srnmb 0 # encoding: [0xb2,0xb8,0x00,0x00] +#CHECK: srnmb 0(%r1) # encoding: [0xb2,0xb8,0x10,0x00] +#CHECK: srnmb 0(%r15) # encoding: [0xb2,0xb8,0xf0,0x00] +#CHECK: srnmb 4095 # encoding: [0xb2,0xb8,0x0f,0xff] +#CHECK: srnmb 4095(%r1) # encoding: [0xb2,0xb8,0x1f,0xff] +#CHECK: srnmb 4095(%r15) # encoding: [0xb2,0xb8,0xff,0xff] + + srnmb 0 + srnmb 0(%r1) + srnmb 0(%r15) + srnmb 4095 + srnmb 4095(%r1) + srnmb 4095(%r15) + #CHECK: stch %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc3] #CHECK: stch %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc3] #CHECK: stch %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc3] diff --git a/test/MC/SystemZ/insn-good.s b/test/MC/SystemZ/insn-good.s index 5e8a93c012a..f3697ca0a15 100644 --- a/test/MC/SystemZ/insn-good.s +++ b/test/MC/SystemZ/insn-good.s @@ -5853,6 +5853,14 @@ ectg 0(%r1),1(%r15),%r2 ectg 0(%r1),4095(%r15),%r2 +#CHECK: efpc %r0 # encoding: [0xb3,0x8c,0x00,0x00] +#CHECK: efpc %r1 # encoding: [0xb3,0x8c,0x00,0x10] +#CHECK: efpc %r15 # encoding: [0xb3,0x8c,0x00,0xf0] + + efpc %r0 + efpc %r1 + efpc %r15 + #CHECK: ex %r0, 0 # encoding: [0x44,0x00,0x00,0x00] #CHECK: ex %r0, 4095 # encoding: [0x44,0x00,0x0f,0xff] #CHECK: ex %r0, 0(%r1) # encoding: [0x44,0x00,0x10,0x00] @@ -6551,6 +6559,34 @@ ley %f0, 524287(%r15,%r1) ley %f15, 0 +#CHECK: lfas 0 # encoding: [0xb2,0xbd,0x00,0x00] +#CHECK: lfas 0(%r1) # encoding: [0xb2,0xbd,0x10,0x00] +#CHECK: lfas 0(%r15) # encoding: [0xb2,0xbd,0xf0,0x00] +#CHECK: lfas 4095 # encoding: [0xb2,0xbd,0x0f,0xff] +#CHECK: lfas 4095(%r1) # encoding: [0xb2,0xbd,0x1f,0xff] +#CHECK: lfas 4095(%r15) # encoding: [0xb2,0xbd,0xff,0xff] + + lfas 0 + lfas 0(%r1) + lfas 0(%r15) + lfas 4095 + lfas 4095(%r1) + lfas 4095(%r15) + +#CHECK: lfpc 0 # encoding: [0xb2,0x9d,0x00,0x00] +#CHECK: lfpc 0(%r1) # encoding: [0xb2,0x9d,0x10,0x00] +#CHECK: lfpc 0(%r15) # encoding: [0xb2,0x9d,0xf0,0x00] +#CHECK: lfpc 4095 # encoding: [0xb2,0x9d,0x0f,0xff] +#CHECK: lfpc 4095(%r1) # encoding: [0xb2,0x9d,0x1f,0xff] +#CHECK: lfpc 4095(%r15) # encoding: [0xb2,0x9d,0xff,0xff] + + lfpc 0 + lfpc 0(%r1) + lfpc 0(%r15) + lfpc 4095 + lfpc 4095(%r1) + lfpc 4095(%r15) + #CHECK: lg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x04] #CHECK: lg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x04] #CHECK: lg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x04] @@ -9153,6 +9189,22 @@ sebr %f7, %f8 sebr %f15, %f0 +#CHECK: sfasr %r0 # encoding: [0xb3,0x85,0x00,0x00] +#CHECK: sfasr %r1 # encoding: [0xb3,0x85,0x00,0x10] +#CHECK: sfasr %r15 # encoding: [0xb3,0x85,0x00,0xf0] + + sfasr %r0 + sfasr %r1 + sfasr %r15 + +#CHECK: sfpc %r0 # encoding: [0xb3,0x84,0x00,0x00] +#CHECK: sfpc %r1 # encoding: [0xb3,0x84,0x00,0x10] +#CHECK: sfpc %r15 # encoding: [0xb3,0x84,0x00,0xf0] + + sfpc %r0 + sfpc %r1 + sfpc %r15 + #CHECK: sg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x09] #CHECK: sg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x09] #CHECK: sg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x09] @@ -9677,6 +9729,34 @@ srlg %r0,%r0,524287(%r1) srlg %r0,%r0,524287(%r15) +#CHECK: srnm 0 # encoding: [0xb2,0x99,0x00,0x00] +#CHECK: srnm 0(%r1) # encoding: [0xb2,0x99,0x10,0x00] +#CHECK: srnm 0(%r15) # encoding: [0xb2,0x99,0xf0,0x00] +#CHECK: srnm 4095 # encoding: [0xb2,0x99,0x0f,0xff] +#CHECK: srnm 4095(%r1) # encoding: [0xb2,0x99,0x1f,0xff] +#CHECK: srnm 4095(%r15) # encoding: [0xb2,0x99,0xff,0xff] + + srnm 0 + srnm 0(%r1) + srnm 0(%r15) + srnm 4095 + srnm 4095(%r1) + srnm 4095(%r15) + +#CHECK: srnmt 0 # encoding: [0xb2,0xb9,0x00,0x00] +#CHECK: srnmt 0(%r1) # encoding: [0xb2,0xb9,0x10,0x00] +#CHECK: srnmt 0(%r15) # encoding: [0xb2,0xb9,0xf0,0x00] +#CHECK: srnmt 4095 # encoding: [0xb2,0xb9,0x0f,0xff] +#CHECK: srnmt 4095(%r1) # encoding: [0xb2,0xb9,0x1f,0xff] +#CHECK: srnmt 4095(%r15) # encoding: [0xb2,0xb9,0xff,0xff] + + srnmt 0 + srnmt 0(%r1) + srnmt 0(%r15) + srnmt 4095 + srnmt 4095(%r1) + srnmt 4095(%r15) + #CHECK: srst %r0, %r0 # encoding: [0xb2,0x5e,0x00,0x00] #CHECK: srst %r0, %r15 # encoding: [0xb2,0x5e,0x00,0x0f] #CHECK: srst %r15, %r0 # encoding: [0xb2,0x5e,0x00,0xf0] @@ -9923,6 +10003,20 @@ stey %f0, 524287(%r15,%r1) stey %f15, 0 +#CHECK: stfpc 0 # encoding: [0xb2,0x9c,0x00,0x00] +#CHECK: stfpc 0(%r1) # encoding: [0xb2,0x9c,0x10,0x00] +#CHECK: stfpc 0(%r15) # encoding: [0xb2,0x9c,0xf0,0x00] +#CHECK: stfpc 4095 # encoding: [0xb2,0x9c,0x0f,0xff] +#CHECK: stfpc 4095(%r1) # encoding: [0xb2,0x9c,0x1f,0xff] +#CHECK: stfpc 4095(%r15) # encoding: [0xb2,0x9c,0xff,0xff] + + stfpc 0 + stfpc 0(%r1) + stfpc 0(%r15) + stfpc 4095 + stfpc 4095(%r1) + stfpc 4095(%r15) + #CHECK: stg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x24] #CHECK: stg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x24] #CHECK: stg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x24] -- 2.50.1