From 48bbdf7673d73d464c248dbded8fc9608c04861a Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 17 Nov 2016 19:21:20 +0000 Subject: [PATCH] Fix spelling mistakes in Hexagon target comments. NFC. Identified by Pedro Giffuni in PR27636. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287248 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 2 +- lib/Target/Hexagon/HexagonExpandCondsets.cpp | 2 +- lib/Target/Hexagon/HexagonHardwareLoops.cpp | 2 +- lib/Target/Hexagon/HexagonInstrFormats.td | 2 +- lib/Target/Hexagon/HexagonInstrFormatsV60.td | 4 ++-- lib/Target/Hexagon/HexagonInstrInfo.cpp | 4 ++-- lib/Target/Hexagon/HexagonInstrInfo.td | 2 +- lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 4 ++-- lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp | 2 +- 9 files changed, 12 insertions(+), 12 deletions(-) diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 36b6e729923..50f529e5b24 100644 --- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -895,7 +895,7 @@ bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) { int64_t MaxBytesToFill = 15; - // if there is an arguement + // if there is an argument if (getLexer().isNot(AsmToken::EndOfStatement)) { const MCExpr *Value; SMLoc ExprLoc = L; diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp index ae940a16b33..a94c9080a56 100644 --- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -1134,7 +1134,7 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { } -/// Attempt to coalesce one of the source registers to a MUX intruction with +/// Attempt to coalesce one of the source registers to a MUX instruction with /// the destination register. This could lead to having only one predicated /// instruction in the end instead of two. bool HexagonExpandCondsets::coalesceSegments( diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 0cc69bb96ba..e72076ed8ac 100644 --- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1514,7 +1514,7 @@ bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO, return false; } - // By now, we should have successfuly obtained the immediate value defining + // By now, we should have successfully obtained the immediate value defining // the register referenced in MO. Handle a potential use of a subregister. switch (MO.getSubReg()) { case Hexagon::isub_lo: diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index fe585ce7ed4..fa3cccbd087 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -54,7 +54,7 @@ class MemAccessSize value> { bits<4> Value = value; } -def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction. +def NoMemAccess : MemAccessSize<0>;// Not a memory access instruction. def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb). def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). def WordAccess : MemAccessSize<3>;// Word access instruction (memw). diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV60.td b/lib/Target/Hexagon/HexagonInstrFormatsV60.td index f3d43dec733..b9f4373a0b7 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV60.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV60.td @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// //----------------------------------------------------------------------------// -// Hexagon Intruction Flags + +// Hexagon Instruction Flags + // // *** Must match BaseInfo.h *** //----------------------------------------------------------------------------// @@ -34,7 +34,7 @@ def TypeCVI_VM_NEW_ST : IType<26>; def TypeCVI_VM_STU : IType<27>; def TypeCVI_HIST : IType<28>; //----------------------------------------------------------------------------// -// Intruction Classes Definitions + +// Instruction Classes Definitions + //----------------------------------------------------------------------------// let validSubTargets = HasV60SubT in diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 65ac1f06916..34ce3e65299 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -2159,7 +2159,7 @@ bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const { } -// Return true if a given MI can accomodate given offset. +// Return true if a given MI can accommodate given offset. // Use abs estimate as oppose to the exact number. // TODO: This will need to be changed to use MC level // definition of instruction extendable field size. @@ -3204,7 +3204,7 @@ bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI, } -// Inserts branching instructions in reverse order of their occurence. +// Inserts branching instructions in reverse order of their occurrence. // e.g. jump_t t1 (i1) // jump t2 (i2) // Jumpers = {i2, i1} diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 97aedaffed2..c5719ad5b6d 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -692,7 +692,7 @@ defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255). -// Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has +// Compiler would want to generate 'zxtb' instead of 'and' because 'zxtb' has // predicated forms while 'and' doesn't. Since integrated assembler can't // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where // immediate operand is set to '255'. diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index c2465bb1371..4292f6b3faa 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -92,7 +92,7 @@ namespace HexagonII { // MemAccessSize is represented as 1+log2(N) where N is size in bits. enum class MemAccessSize { - NoMemAccess = 0, // Not a memory acces instruction. + NoMemAccess = 0, // Not a memory access instruction. ByteAccess = 1, // Byte access instruction (memb). HalfWordAccess = 2, // Half word access instruction (memh). WordAccess = 3, // Word access instruction (memw). @@ -201,7 +201,7 @@ namespace HexagonII { AccumulatorPos = 54, AccumulatorMask = 0x1, - // Complex XU, prevent xu competition by prefering slot3 + // Complex XU, prevent xu competition by preferring slot3 PrefersSlot3Pos = 55, PrefersSlot3Mask = 0x1, diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index 4c508d6d29e..413f052aa4b 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -1016,7 +1016,7 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, k = j + distance; (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) { - // Check if reversable. + // Check if reversible. bool bisReversable = true; if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) && isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) { -- 2.40.0