From 460a780d4f140cc74e12a14b312c618e6d37b095 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 14 Nov 2016 01:53:29 +0000 Subject: [PATCH] [X86] Cleanup 'x' and 'y' mnemonic suffixes for vcvtpd2dq/vcvttpd2dq/vcvtpd2ps and similar instructions. -Don't print the 'x' suffix for the 128-bit reg/mem VEX encoded instructions in Intel syntax. This is consistent with the EVEX versions. -Don't print the 'y' suffix for the 256-bit reg/reg VEX encoded instructions in Intel or AT&T syntax. This is consistent with the EVEX versions. -Allow the 'x' and 'y' suffixes to be used for the reg/mem forms when we're assembling using Intel syntax. -Allow the 'x' and 'y' suffixes on the reg/reg EVEX encoded instructions in Intel or AT&T syntax. This is consistent with what VEX was already allowing. This should fix at least some of PR28850. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286787 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrAVX512.td | 36 +++ lib/Target/X86/X86InstrInfo.cpp | 6 +- lib/Target/X86/X86InstrSSE.td | 52 +++-- test/CodeGen/X86/avx-cvt.ll | 6 +- test/CodeGen/X86/avx-fp2int.ll | 4 +- test/CodeGen/X86/avx-intrinsics-fast-isel.ll | 12 +- test/CodeGen/X86/avx-intrinsics-x86.ll | 6 +- test/CodeGen/X86/avx512-cvt.ll | 28 +-- test/CodeGen/X86/combine-fcopysign.ll | 2 +- test/CodeGen/X86/fp-trunc.ll | 6 +- test/CodeGen/X86/vec_fp_to_int.ll | 44 +--- test/MC/X86/intel-syntax-x86-64-avx.s | 96 ++++++++ test/MC/X86/intel-syntax-x86-64-avx512f_vl.s | 225 ++++++++++++++++++- test/MC/X86/x86-32-avx.s | 14 +- test/MC/X86/x86_64-avx-encoding.s | 12 +- 15 files changed, 442 insertions(+), 107 deletions(-) diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index f793c26090b..71748d37dbe 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -6152,6 +6152,15 @@ multiclass avx512_cvtpd2ps opc, string OpcodeStr> { X86vfpround, "{1to2}", "{x}">, EVEX_V128; defm Z256 : avx512_vcvt_fp, EVEX_V256; + + def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + def : InstAlias(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0>; + def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + def : InstAlias(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0>; } } @@ -6255,6 +6264,15 @@ multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDNode OpNode, OpNode128, "{1to2}", "{x}">, EVEX_V128; defm Z256 : avx512_vcvt_fp, EVEX_V256; + + def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + def : InstAlias(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0>; + def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + def : InstAlias(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0>; } } @@ -6275,6 +6293,15 @@ multiclass avx512_cvtpd2dq opc, string OpcodeStr, "{1to2}", "{x}">, EVEX_V128; defm Z256 : avx512_vcvt_fp, EVEX_V256; + + def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + def : InstAlias(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0>; + def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + def : InstAlias(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0>; } } @@ -6379,6 +6406,15 @@ multiclass avx512_cvtqq2ps opc, string OpcodeStr, "{1to2}", "{x}">, EVEX_V128; defm Z256 : avx512_vcvt_fp, EVEX_V256; + + def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + def : InstAlias(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0>; + def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + def : InstAlias(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0>; } } diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index cb1861934de..c4a9684b3e5 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -641,11 +641,11 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 }, { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 }, - { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 }, - { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 }, + { X86::VCVTPD2DQrr, X86::VCVTPD2DQrm, 0 }, + { X86::VCVTPD2PSrr, X86::VCVTPD2PSrm, 0 }, { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 }, { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 }, - { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 }, + { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, 0 }, { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 }, { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index d9580565850..3eb87fd9ed9 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -1970,15 +1970,17 @@ def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), // XMM only def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}", (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>; -def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), - "vcvtpd2dqx\t{$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v4i32 (X86cvtp2Int (loadv2f64 addr:$src))))]>, VEX, - Sched<[WriteCvtF2ILd]>; +def VCVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "vcvtpd2dq{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (loadv2f64 addr:$src))))]>, VEX, + Sched<[WriteCvtF2ILd]>; +def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}", + (VCVTPD2DQrm VR128:$dst, f128mem:$src), 0>; // YMM only def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), - "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", + "vcvtpd2dq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (v4i32 (X86cvtp2Int (v4f64 VR256:$src))))]>, VEX, VEX_L, Sched<[WriteCvtF2I]>; @@ -1987,8 +1989,10 @@ def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), [(set VR128:$dst, (v4i32 (X86cvtp2Int (loadv4f64 addr:$src))))]>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>; -def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}", +def : InstAlias<"vcvtpd2dqy\t{$src, $dst|$dst, $src}", (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>; +def : InstAlias<"vcvtpd2dqy\t{$src, $dst|$dst, $src}", + (VCVTPD2DQYrm VR128:$dst, f256mem:$src), 0>; } def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), @@ -2054,16 +2058,18 @@ def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}", (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>; let Predicates = [HasAVX, NoVLX] in -def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), - "cvttpd2dqx\t{$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v4i32 (X86cvttpd2dq (loadv2f64 addr:$src))))], - IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>; +def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvttpd2dq{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttpd2dq (loadv2f64 addr:$src))))], + IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>; +def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}", + (VCVTTPD2DQrm VR128:$dst, f128mem:$src), 0>; // YMM only let Predicates = [HasAVX, NoVLX] in { def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), - "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", + "cvttpd2dq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (v4i32 (fp_to_sint (v4f64 VR256:$src))))], IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>; @@ -2073,8 +2079,10 @@ def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), (v4i32 (fp_to_sint (loadv4f64 addr:$src))))], IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>; } -def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}", +def : InstAlias<"vcvttpd2dqy\t{$src, $dst|$dst, $src}", (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>; +def : InstAlias<"vcvttpd2dqy\t{$src, $dst|$dst, $src}", + (VCVTTPD2DQYrm VR128:$dst, f256mem:$src), 0>; let Predicates = [HasAVX, NoVLX] in { let AddedComplexity = 15 in @@ -2196,15 +2204,17 @@ def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}", (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>; let Predicates = [HasAVX, NoVLX] in -def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), - "cvtpd2psx\t{$src, $dst|$dst, $src}", - [(set VR128:$dst, (X86vfpround (loadv2f64 addr:$src)))], - IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>; +def VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtpd2ps{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (loadv2f64 addr:$src)))], + IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>; +def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}", + (VCVTPD2PSrm VR128:$dst, f128mem:$src), 0>; // YMM only let Predicates = [HasAVX, NoVLX] in { def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), - "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", + "cvtpd2ps\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (fpround VR256:$src))], IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>; def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), @@ -2212,8 +2222,10 @@ def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), [(set VR128:$dst, (fpround (loadv4f64 addr:$src)))], IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>; } -def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}", +def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}", (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>; +def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}", + (VCVTPD2PSYrm VR128:$dst, f256mem:$src), 0>; def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtpd2ps\t{$src, $dst|$dst, $src}", diff --git a/test/CodeGen/X86/avx-cvt.ll b/test/CodeGen/X86/avx-cvt.ll index 27339898efd..c8e806890d0 100644 --- a/test/CodeGen/X86/avx-cvt.ll +++ b/test/CodeGen/X86/avx-cvt.ll @@ -44,7 +44,7 @@ define <8 x float> @sitofp02(<8 x i16> %a) { define <4 x i32> @fptosi01(<4 x double> %a) { ; CHECK-LABEL: fptosi01: ; CHECK: # BB#0: -; CHECK-NEXT: vcvttpd2dqy %ymm0, %xmm0 +; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %b = fptosi <4 x double> %a to <4 x i32> @@ -54,8 +54,8 @@ define <4 x i32> @fptosi01(<4 x double> %a) { define <8 x float> @fptrunc00(<8 x double> %b) nounwind { ; CHECK-LABEL: fptrunc00: ; CHECK: # BB#0: -; CHECK-NEXT: vcvtpd2psy %ymm0, %xmm0 -; CHECK-NEXT: vcvtpd2psy %ymm1, %xmm1 +; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm0 +; CHECK-NEXT: vcvtpd2ps %ymm1, %xmm1 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: retq %a = fptrunc <8 x double> %b to <8 x float> diff --git a/test/CodeGen/X86/avx-fp2int.ll b/test/CodeGen/X86/avx-fp2int.ll index 8beaac6a780..f06564b0f58 100644 --- a/test/CodeGen/X86/avx-fp2int.ll +++ b/test/CodeGen/X86/avx-fp2int.ll @@ -3,10 +3,10 @@ ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate ; CHECK-LABEL: test1: -; CHECK: vcvttpd2dqy +; CHECK: vcvttpd2dq ; CHECK: ret ; CHECK-LABEL: test2: -; CHECK: vcvttpd2dqy +; CHECK: vcvttpd2dq ; CHECK: ret define <4 x i8> @test1(<4 x double> %d) { diff --git a/test/CodeGen/X86/avx-intrinsics-fast-isel.ll b/test/CodeGen/X86/avx-intrinsics-fast-isel.ll index 079a57ef6b5..fe4fc65ef71 100644 --- a/test/CodeGen/X86/avx-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/avx-intrinsics-fast-isel.ll @@ -605,13 +605,13 @@ declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone define <2 x i64> @test_mm256_cvtpd_epi32(<4 x double> %a0) nounwind { ; X32-LABEL: test_mm256_cvtpd_epi32: ; X32: # BB#0: -; X32-NEXT: vcvtpd2dqy %ymm0, %xmm0 +; X32-NEXT: vcvtpd2dq %ymm0, %xmm0 ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_cvtpd_epi32: ; X64: # BB#0: -; X64-NEXT: vcvtpd2dqy %ymm0, %xmm0 +; X64-NEXT: vcvtpd2dq %ymm0, %xmm0 ; X64-NEXT: vzeroupper ; X64-NEXT: retq %cvt = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> %a0) @@ -623,13 +623,13 @@ declare <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double>) nounwind readnone define <4 x float> @test_mm256_cvtpd_ps(<4 x double> %a0) nounwind { ; X32-LABEL: test_mm256_cvtpd_ps: ; X32: # BB#0: -; X32-NEXT: vcvtpd2psy %ymm0, %xmm0 +; X32-NEXT: vcvtpd2ps %ymm0, %xmm0 ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_cvtpd_ps: ; X64: # BB#0: -; X64-NEXT: vcvtpd2psy %ymm0, %xmm0 +; X64-NEXT: vcvtpd2ps %ymm0, %xmm0 ; X64-NEXT: vzeroupper ; X64-NEXT: retq %res = call <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double> %a0) @@ -670,13 +670,13 @@ define <4 x double> @test_mm256_cvtps_pd(<4 x float> %a0) nounwind { define <2 x i64> @test_mm256_cvttpd_epi32(<4 x double> %a0) nounwind { ; X32-LABEL: test_mm256_cvttpd_epi32: ; X32: # BB#0: -; X32-NEXT: vcvttpd2dqy %ymm0, %xmm0 +; X32-NEXT: vcvttpd2dq %ymm0, %xmm0 ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_cvttpd_epi32: ; X64: # BB#0: -; X64-NEXT: vcvttpd2dqy %ymm0, %xmm0 +; X64-NEXT: vcvttpd2dq %ymm0, %xmm0 ; X64-NEXT: vzeroupper ; X64-NEXT: retq %cvt = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index ce4034594e4..fb92f25b3ba 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -2833,7 +2833,7 @@ declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounw define <4 x float> @test_x86_avx_cvt_pd2_ps_256(<4 x double> %a0) { ; AVX-LABEL: test_x86_avx_cvt_pd2_ps_256: ; AVX: ## BB#0: -; AVX-NEXT: vcvtpd2psy %ymm0, %xmm0 ## encoding: [0xc5,0xfd,0x5a,0xc0] +; AVX-NEXT: vcvtpd2ps %ymm0, %xmm0 ## encoding: [0xc5,0xfd,0x5a,0xc0] ; AVX-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; AVX-NEXT: retl ## encoding: [0xc3] ; @@ -2850,7 +2850,7 @@ declare <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double>) nounwind readnone define <4 x i32> @test_x86_avx_cvt_pd2dq_256(<4 x double> %a0) { ; AVX-LABEL: test_x86_avx_cvt_pd2dq_256: ; AVX: ## BB#0: -; AVX-NEXT: vcvtpd2dqy %ymm0, %xmm0 ## encoding: [0xc5,0xff,0xe6,0xc0] +; AVX-NEXT: vcvtpd2dq %ymm0, %xmm0 ## encoding: [0xc5,0xff,0xe6,0xc0] ; AVX-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; AVX-NEXT: retl ## encoding: [0xc3] ; @@ -2894,7 +2894,7 @@ declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) { ; AVX-LABEL: test_x86_avx_cvtt_pd2dq_256: ; AVX: ## BB#0: -; AVX-NEXT: vcvttpd2dqy %ymm0, %xmm0 ## encoding: [0xc5,0xfd,0xe6,0xc0] +; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0 ## encoding: [0xc5,0xfd,0xe6,0xc0] ; AVX-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; AVX-NEXT: retl ## encoding: [0xc3] ; diff --git a/test/CodeGen/X86/avx512-cvt.ll b/test/CodeGen/X86/avx512-cvt.ll index ff4270a283d..c370b79008c 100644 --- a/test/CodeGen/X86/avx512-cvt.ll +++ b/test/CodeGen/X86/avx512-cvt.ll @@ -361,15 +361,10 @@ define <8 x i32> @fptosi01(<8 x double> %a) { } define <4 x i32> @fptosi03(<4 x double> %a) { -; KNL-LABEL: fptosi03: -; KNL: ## BB#0: -; KNL-NEXT: vcvttpd2dqy %ymm0, %xmm0 -; KNL-NEXT: retq -; -; SKX-LABEL: fptosi03: -; SKX: ## BB#0: -; SKX-NEXT: vcvttpd2dq %ymm0, %xmm0 -; SKX-NEXT: retq +; ALL-LABEL: fptosi03: +; ALL: ## BB#0: +; ALL-NEXT: vcvttpd2dq %ymm0, %xmm0 +; ALL-NEXT: retq %b = fptosi <4 x double> %a to <4 x i32> ret <4 x i32> %b } @@ -393,15 +388,10 @@ define <16 x float> @fptrunc00(<16 x double> %b) nounwind { } define <4 x float> @fptrunc01(<4 x double> %b) { -; KNL-LABEL: fptrunc01: -; KNL: ## BB#0: -; KNL-NEXT: vcvtpd2psy %ymm0, %xmm0 -; KNL-NEXT: retq -; -; SKX-LABEL: fptrunc01: -; SKX: ## BB#0: -; SKX-NEXT: vcvtpd2ps %ymm0, %xmm0 -; SKX-NEXT: retq +; ALL-LABEL: fptrunc01: +; ALL: ## BB#0: +; ALL-NEXT: vcvtpd2ps %ymm0, %xmm0 +; ALL-NEXT: retq %a = fptrunc <4 x double> %b to <4 x float> ret <4 x float> %a } @@ -411,7 +401,7 @@ define <4 x float> @fptrunc02(<4 x double> %b, <4 x i1> %mask) { ; KNL: ## BB#0: ; KNL-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL-NEXT: vpsrad $31, %xmm1, %xmm1 -; KNL-NEXT: vcvtpd2psy %ymm0, %xmm0 +; KNL-NEXT: vcvtpd2ps %ymm0, %xmm0 ; KNL-NEXT: vpand %xmm0, %xmm1, %xmm0 ; KNL-NEXT: retq ; diff --git a/test/CodeGen/X86/combine-fcopysign.ll b/test/CodeGen/X86/combine-fcopysign.ll index 1c559ffd0aa..807ac4e3fc6 100644 --- a/test/CodeGen/X86/combine-fcopysign.ll +++ b/test/CodeGen/X86/combine-fcopysign.ll @@ -315,7 +315,7 @@ define <4 x float> @combine_vec_fcopysign_fptrunc_sgn(<4 x float> %x, <4 x doubl ; AVX: # BB#0: ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm2 ; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vcvtpd2psy %ymm1, %xmm1 +; AVX-NEXT: vcvtpd2ps %ymm1, %xmm1 ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm2 ; AVX-NEXT: vandpd %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0 diff --git a/test/CodeGen/X86/fp-trunc.ll b/test/CodeGen/X86/fp-trunc.ll index b1ffd5a6530..2f700cd4cc7 100644 --- a/test/CodeGen/X86/fp-trunc.ll +++ b/test/CodeGen/X86/fp-trunc.ll @@ -50,7 +50,7 @@ define <4 x float> @test3(<4 x double> %x) nounwind { ; ; AVX-LABEL: test3: ; AVX: # BB#0: -; AVX-NEXT: vcvtpd2psy %ymm0, %xmm0 +; AVX-NEXT: vcvtpd2ps %ymm0, %xmm0 ; AVX-NEXT: vzeroupper ; AVX-NEXT: retl %y = fptrunc <4 x double> %x to <4 x float> @@ -72,8 +72,8 @@ define <8 x float> @test4(<8 x double> %x) nounwind { ; ; AVX-LABEL: test4: ; AVX: # BB#0: -; AVX-NEXT: vcvtpd2psy %ymm0, %xmm0 -; AVX-NEXT: vcvtpd2psy %ymm1, %xmm1 +; AVX-NEXT: vcvtpd2ps %ymm0, %xmm0 +; AVX-NEXT: vcvtpd2ps %ymm1, %xmm1 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: retl %y = fptrunc <8 x double> %x to <8 x float> diff --git a/test/CodeGen/X86/vec_fp_to_int.ll b/test/CodeGen/X86/vec_fp_to_int.ll index 2b5bf8fffa8..2e9fababef1 100644 --- a/test/CodeGen/X86/vec_fp_to_int.ll +++ b/test/CodeGen/X86/vec_fp_to_int.ll @@ -117,27 +117,15 @@ define <4 x i32> @fptosi_4f64_to_2i32(<2 x double> %a) { ; AVX-LABEL: fptosi_4f64_to_2i32: ; AVX: # BB#0: ; AVX-NEXT: # kill: %XMM0 %XMM0 %YMM0 -; AVX-NEXT: vcvttpd2dqy %ymm0, %xmm0 +; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0 ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq ; -; AVX512F-LABEL: fptosi_4f64_to_2i32: -; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0 %XMM0 %YMM0 -; AVX512F-NEXT: vcvttpd2dqy %ymm0, %xmm0 -; AVX512F-NEXT: retq -; -; AVX512VL-LABEL: fptosi_4f64_to_2i32: -; AVX512VL: # BB#0: -; AVX512VL-NEXT: # kill: %XMM0 %XMM0 %YMM0 -; AVX512VL-NEXT: vcvttpd2dq %ymm0, %xmm0 -; AVX512VL-NEXT: retq -; -; AVX512VLDQ-LABEL: fptosi_4f64_to_2i32: -; AVX512VLDQ: # BB#0: -; AVX512VLDQ-NEXT: # kill: %XMM0 %XMM0 %YMM0 -; AVX512VLDQ-NEXT: vcvttpd2dq %ymm0, %xmm0 -; AVX512VLDQ-NEXT: retq +; AVX512-LABEL: fptosi_4f64_to_2i32: +; AVX512: # BB#0: +; AVX512-NEXT: # kill: %XMM0 %XMM0 %YMM0 +; AVX512-NEXT: vcvttpd2dq %ymm0, %xmm0 +; AVX512-NEXT: retq %ext = shufflevector <2 x double> %a, <2 x double> undef, <4 x i32> %cvt = fptosi <4 x double> %ext to <4 x i32> ret <4 x i32> %cvt @@ -252,24 +240,14 @@ define <4 x i32> @fptosi_4f64_to_4i32(<4 x double> %a) { ; ; AVX-LABEL: fptosi_4f64_to_4i32: ; AVX: # BB#0: -; AVX-NEXT: vcvttpd2dqy %ymm0, %xmm0 +; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0 ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq ; -; AVX512F-LABEL: fptosi_4f64_to_4i32: -; AVX512F: # BB#0: -; AVX512F-NEXT: vcvttpd2dqy %ymm0, %xmm0 -; AVX512F-NEXT: retq -; -; AVX512VL-LABEL: fptosi_4f64_to_4i32: -; AVX512VL: # BB#0: -; AVX512VL-NEXT: vcvttpd2dq %ymm0, %xmm0 -; AVX512VL-NEXT: retq -; -; AVX512VLDQ-LABEL: fptosi_4f64_to_4i32: -; AVX512VLDQ: # BB#0: -; AVX512VLDQ-NEXT: vcvttpd2dq %ymm0, %xmm0 -; AVX512VLDQ-NEXT: retq +; AVX512-LABEL: fptosi_4f64_to_4i32: +; AVX512: # BB#0: +; AVX512-NEXT: vcvttpd2dq %ymm0, %xmm0 +; AVX512-NEXT: retq %cvt = fptosi <4 x double> %a to <4 x i32> ret <4 x i32> %cvt } diff --git a/test/MC/X86/intel-syntax-x86-64-avx.s b/test/MC/X86/intel-syntax-x86-64-avx.s index eff0974c1a0..3139fc431ae 100644 --- a/test/MC/X86/intel-syntax-x86-64-avx.s +++ b/test/MC/X86/intel-syntax-x86-64-avx.s @@ -63,3 +63,99 @@ // CHECK: vpgatherqd xmm10, xmmword ptr [r15 + 2*ymm9], xmm8 // CHECK: encoding: [0xc4,0x02,0x3d,0x91,0x14,0x4f] vpgatherqd xmm10, xmmword ptr [r15 + 2*ymm9], xmm8 + +// CHECK: vcvtpd2ps xmm0, xmm15 +// CHECK: encoding: [0xc4,0xc1,0x79,0x5a,0xc7] + vcvtpd2ps xmm0, xmm15 + +// CHECK: vcvtpd2ps xmm0, xmm15 +// CHECK: encoding: [0xc4,0xc1,0x79,0x5a,0xc7] + vcvtpd2psx xmm0, xmm15 + +// CHECK: vcvtpd2ps xmm0, xmmword ptr [rax] +// CHECK: encoding: [0xc5,0xf9,0x5a,0x00] + vcvtpd2ps xmm0, xmmword ptr [rax] + +// CHECK: vcvtpd2ps xmm0, xmmword ptr [rax] +// CHECK: encoding: [0xc5,0xf9,0x5a,0x00] + vcvtpd2psx xmm0, xmmword ptr [rax] + +// CHECK: vcvtpd2ps xmm0, ymm15 +// CHECK: encoding: [0xc4,0xc1,0x7d,0x5a,0xc7] + vcvtpd2ps xmm0, ymm15 + +// CHECK: vcvtpd2ps xmm0, ymm15 +// CHECK: encoding: [0xc4,0xc1,0x7d,0x5a,0xc7] + vcvtpd2psy xmm0, ymm15 + +// CHECK: vcvtpd2ps xmm0, ymmword ptr [rax] +// CHECK: encoding: [0xc5,0xfd,0x5a,0x00] + vcvtpd2ps xmm0, ymmword ptr [rax] + +// CHECK: vcvtpd2ps xmm0, ymmword ptr [rax] +// CHECK: encoding: [0xc5,0xfd,0x5a,0x00] + vcvtpd2psy xmm0, ymmword ptr [rax] + +// CHECK: vcvtpd2dq xmm0, xmm15 +// CHECK: encoding: [0xc4,0xc1,0x7b,0xe6,0xc7] + vcvtpd2dq xmm0, xmm15 + +// CHECK: vcvtpd2dq xmm0, xmm15 +// CHECK: encoding: [0xc4,0xc1,0x7b,0xe6,0xc7] + vcvtpd2dqx xmm0, xmm15 + +// CHECK: vcvtpd2dq xmm0, xmmword ptr [rax] +// CHECK: encoding: [0xc5,0xfb,0xe6,0x00] + vcvtpd2dq xmm0, xmmword ptr [rax] + +// CHECK: vcvtpd2dq xmm0, xmmword ptr [rax] +// CHECK: encoding: [0xc5,0xfb,0xe6,0x00] + vcvtpd2dqx xmm0, xmmword ptr [rax] + +// CHECK: vcvtpd2dq xmm0, ymm15 +// CHECK: encoding: [0xc4,0xc1,0x7f,0xe6,0xc7] + vcvtpd2dq xmm0, ymm15 + +// CHECK: vcvtpd2dq xmm0, ymm15 +// CHECK: encoding: [0xc4,0xc1,0x7f,0xe6,0xc7] + vcvtpd2dqy xmm0, ymm15 + +// CHECK: vcvtpd2dq xmm0, ymmword ptr [rax] +// CHECK: encoding: [0xc5,0xff,0xe6,0x00] + vcvtpd2dq xmm0, ymmword ptr [rax] + +// CHECK: vcvtpd2dq xmm0, ymmword ptr [rax] +// CHECK: encoding: [0xc5,0xff,0xe6,0x00] + vcvtpd2dqy xmm0, ymmword ptr [rax] + +// CHECK: vcvttpd2dq xmm0, xmm15 +// CHECK: encoding: [0xc4,0xc1,0x79,0xe6,0xc7] + vcvttpd2dq xmm0, xmm15 + +// CHECK: vcvttpd2dq xmm0, xmm15 +// CHECK: encoding: [0xc4,0xc1,0x79,0xe6,0xc7] + vcvttpd2dqx xmm0, xmm15 + +// CHECK: vcvttpd2dq xmm0, xmmword ptr [rax] +// CHECK: encoding: [0xc5,0xf9,0xe6,0x00] + vcvttpd2dq xmm0, xmmword ptr [rax] + +// CHECK: vcvttpd2dq xmm0, xmmword ptr [rax] +// CHECK: encoding: [0xc5,0xf9,0xe6,0x00] + vcvttpd2dqx xmm0, xmmword ptr [rax] + +// CHECK: vcvttpd2dq xmm0, ymm15 +// CHECK: encoding: [0xc4,0xc1,0x7d,0xe6,0xc7] + vcvttpd2dq xmm0, ymm15 + +// CHECK: vcvttpd2dq xmm0, ymm15 +// CHECK: encoding: [0xc4,0xc1,0x7d,0xe6,0xc7] + vcvttpd2dqy xmm0, ymm15 + +// CHECK: vcvttpd2dq xmm0, ymmword ptr [rax] +// CHECK: encoding: [0xc5,0xfd,0xe6,0x00] + vcvttpd2dq xmm0, ymmword ptr [rax] + +// CHECK: vcvttpd2dq xmm0, ymmword ptr [rax] +// CHECK: encoding: [0xc5,0xfd,0xe6,0x00] + vcvttpd2dqy xmm0, ymmword ptr [rax] diff --git a/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s b/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s index caff5978d5d..4f4c6d15df6 100644 --- a/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s +++ b/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl -mattr=+avx512vl -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s +// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl -mattr=+avx512vl,+avx512dq -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s // CHECK: vcmppd k3, xmm27, xmm23, 171 // CHECK: encoding: [0x62,0xb1,0xa5,0x00,0xc2,0xdf,0xab] @@ -1120,3 +1120,226 @@ // CHECK: encoding: [0x62,0xa2,0x7d,0x21,0xa3,0xbc,0xb9,0x00,0x04,0x00,0x00] vscatterqps xmmword ptr [rcx + 4*ymm31 + 1024] {k1}, xmm23 +// CHECK: vcvtpd2ps xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0x5a,0xc7] + vcvtpd2ps xmm0, xmm23 + +// CHECK: vcvtpd2ps xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0x5a,0xc7] + vcvtpd2psx xmm0, xmm23 + +// CHECK: vcvtpd2ps xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x5a,0x00] + vcvtpd2ps xmm16, xmmword ptr [rax] + +// CHECK: vcvtpd2ps xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x5a,0x00] + vcvtpd2psx xmm16, xmmword ptr [rax] + +// CHECK: vcvtpd2ps xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfd,0x28,0x5a,0xc7] + vcvtpd2ps xmm0, ymm23 + +// CHECK: vcvtpd2ps xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfd,0x28,0x5a,0xc7] + vcvtpd2psy xmm0, ymm23 + +// CHECK: vcvtpd2ps xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x5a,0x00] + vcvtpd2ps xmm16, ymmword ptr [rax] + +// CHECK: vcvtpd2ps xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x5a,0x00] + vcvtpd2psy xmm16, ymmword ptr [rax] + +// CHECK: vcvtpd2dq xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xff,0x08,0xe6,0xc7] + vcvtpd2dq xmm0, xmm23 + +// CHECK: vcvtpd2dq xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xff,0x08,0xe6,0xc7] + vcvtpd2dqx xmm0, xmm23 + +// CHECK: vcvtpd2dq xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xff,0x08,0xe6,0x00] + vcvtpd2dq xmm16, xmmword ptr [rax] + +// CHECK: vcvtpd2dq xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xff,0x08,0xe6,0x00] + vcvtpd2dqx xmm16, xmmword ptr [rax] + +// CHECK: vcvtpd2dq xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xff,0x28,0xe6,0xc7] + vcvtpd2dq xmm0, ymm23 + +// CHECK: vcvtpd2dq xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xff,0x28,0xe6,0xc7] + vcvtpd2dqy xmm0, ymm23 + +// CHECK: vcvtpd2dq xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xff,0x28,0xe6,0x00] + vcvtpd2dq xmm16, ymmword ptr [rax] + +// CHECK: vcvtpd2dq xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xff,0x28,0xe6,0x00] + vcvtpd2dqy xmm16, ymmword ptr [rax] + +// CHECK: vcvtpd2udq xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x79,0xc7] + vcvtpd2udq xmm0, xmm23 + +// CHECK: vcvtpd2udq xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x79,0xc7] + vcvtpd2udqx xmm0, xmm23 + +// CHECK: vcvtpd2udq xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x79,0x00] + vcvtpd2udq xmm16, xmmword ptr [rax] + +// CHECK: vcvtpd2udq xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x79,0x00] + vcvtpd2udqx xmm16, xmmword ptr [rax] + +// CHECK: vcvtpd2udq xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x79,0xc7] + vcvtpd2udq xmm0, ymm23 + +// CHECK: vcvtpd2udq xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x79,0xc7] + vcvtpd2udqy xmm0, ymm23 + +// CHECK: vcvtpd2udq xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x79,0x00] + vcvtpd2udq xmm16, ymmword ptr [rax] + +// CHECK: vcvtpd2udq xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x79,0x00] + vcvtpd2udqy xmm16, ymmword ptr [rax] + +// CHECK: vcvttpd2dq xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0xe6,0xc7] + vcvttpd2dq xmm0, xmm23 + +// CHECK: vcvttpd2dq xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0xe6,0xc7] + vcvttpd2dqx xmm0, xmm23 + +// CHECK: vcvttpd2dq xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0xe6,0x00] + vcvttpd2dq xmm16, xmmword ptr [rax] + +// CHECK: vcvttpd2dq xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0xe6,0x00] + vcvttpd2dqx xmm16, xmmword ptr [rax] + +// CHECK: vcvttpd2dq xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfd,0x28,0xe6,0xc7] + vcvttpd2dq xmm0, ymm23 + +// CHECK: vcvttpd2dq xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfd,0x28,0xe6,0xc7] + vcvttpd2dqy xmm0, ymm23 + +// CHECK: vcvttpd2dq xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0xe6,0x00] + vcvttpd2dq xmm16, ymmword ptr [rax] + +// CHECK: vcvttpd2dq xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0xe6,0x00] + vcvttpd2dqy xmm16, ymmword ptr [rax] + +// CHECK: vcvttpd2udq xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x78,0xc7] + vcvttpd2udq xmm0, xmm23 + +// CHECK: vcvttpd2udq xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x78,0xc7] + vcvttpd2udqx xmm0, xmm23 + +// CHECK: vcvttpd2udq xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x78,0x00] + vcvttpd2udq xmm16, xmmword ptr [rax] + +// CHECK: vcvttpd2udq xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x78,0x00] + vcvttpd2udqx xmm16, xmmword ptr [rax] + +// CHECK: vcvttpd2udq xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x78,0xc7] + vcvttpd2udq xmm0, ymm23 + +// CHECK: vcvttpd2udq xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x78,0xc7] + vcvttpd2udqy xmm0, ymm23 + +// CHECK: vcvttpd2udq xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x78,0x00] + vcvttpd2udq xmm16, ymmword ptr [rax] + +// CHECK: vcvttpd2udq xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x78,0x00] + vcvttpd2udqy xmm16, ymmword ptr [rax] + +// CHECK: vcvtqq2ps xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x5b,0xc7] + vcvtqq2ps xmm0, xmm23 + +// CHECK: vcvtqq2ps xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x5b,0xc7] + vcvtqq2psx xmm0, xmm23 + +// CHECK: vcvtqq2ps xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x5b,0x00] + vcvtqq2ps xmm16, xmmword ptr [rax] + +// CHECK: vcvtqq2ps xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x5b,0x00] + vcvtqq2psx xmm16, xmmword ptr [rax] + +// CHECK: vcvtqq2ps xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x5b,0xc7] + vcvtqq2ps xmm0, ymm23 + +// CHECK: vcvtqq2ps xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x5b,0xc7] + vcvtqq2psy xmm0, ymm23 + +// CHECK: vcvtqq2ps xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x5b,0x00] + vcvtqq2ps xmm16, ymmword ptr [rax] + +// CHECK: vcvtqq2ps xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x5b,0x00] + vcvtqq2psy xmm16, ymmword ptr [rax] + +// CHECK: vcvtuqq2ps xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x7a,0xc7] + vcvtuqq2ps xmm0, xmm23 + +// CHECK: vcvtuqq2ps xmm0, xmm23 +// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x7a,0xc7] + vcvtuqq2psx xmm0, xmm23 + +// CHECK: vcvtuqq2ps xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0x00] + vcvtuqq2ps xmm16, xmmword ptr [rax] + +// CHECK: vcvtuqq2ps xmm16, xmmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0x00] + vcvtuqq2psx xmm16, xmmword ptr [rax] + +// CHECK: vcvtuqq2ps xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xff,0x28,0x7a,0xc7] + vcvtuqq2ps xmm0, ymm23 + +// CHECK: vcvtuqq2ps xmm0, ymm23 +// CHECK: encoding: [0x62,0xb1,0xff,0x28,0x7a,0xc7] + vcvtuqq2psy xmm0, ymm23 + +// CHECK: vcvtuqq2ps xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x7a,0x00] + vcvtuqq2ps xmm16, ymmword ptr [rax] + +// CHECK: vcvtuqq2ps xmm16, ymmword ptr [rax] +// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x7a,0x00] + vcvtuqq2psy xmm16, ymmword ptr [rax] diff --git a/test/MC/X86/x86-32-avx.s b/test/MC/X86/x86-32-avx.s index a2f47d45d8a..65ebb3f660f 100644 --- a/test/MC/X86/x86-32-avx.s +++ b/test/MC/X86/x86-32-avx.s @@ -2627,19 +2627,19 @@ // CHECK: encoding: [0xc5,0xf9,0xe6,0xe9] vcvttpd2dq %xmm1, %xmm5 -// CHECK: vcvttpd2dqy %ymm2, %xmm5 +// CHECK: vcvttpd2dq %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xfd,0xe6,0xea] vcvttpd2dq %ymm2, %xmm5 // CHECK: vcvttpd2dq %xmm1, %xmm5 // CHECK: encoding: [0xc5,0xf9,0xe6,0xe9] - vcvttpd2dqx %xmm1, %xmm5 + vcvttpd2dq %xmm1, %xmm5 // CHECK: vcvttpd2dqx (%eax), %xmm1 // CHECK: encoding: [0xc5,0xf9,0xe6,0x08] vcvttpd2dqx (%eax), %xmm1 -// CHECK: vcvttpd2dqy %ymm2, %xmm1 +// CHECK: vcvttpd2dq %ymm2, %xmm1 // CHECK: encoding: [0xc5,0xfd,0xe6,0xca] vcvttpd2dqy %ymm2, %xmm1 @@ -2647,7 +2647,7 @@ // CHECK: encoding: [0xc5,0xfd,0xe6,0x08] vcvttpd2dqy (%eax), %xmm1 -// CHECK: vcvtpd2psy %ymm2, %xmm5 +// CHECK: vcvtpd2ps %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xfd,0x5a,0xea] vcvtpd2ps %ymm2, %xmm5 @@ -2659,7 +2659,7 @@ // CHECK: encoding: [0xc5,0xf9,0x5a,0x08] vcvtpd2psx (%eax), %xmm1 -// CHECK: vcvtpd2psy %ymm2, %xmm1 +// CHECK: vcvtpd2ps %ymm2, %xmm1 // CHECK: encoding: [0xc5,0xfd,0x5a,0xca] vcvtpd2psy %ymm2, %xmm1 @@ -2667,11 +2667,11 @@ // CHECK: encoding: [0xc5,0xfd,0x5a,0x08] vcvtpd2psy (%eax), %xmm1 -// CHECK: vcvtpd2dqy %ymm2, %xmm5 +// CHECK: vcvtpd2dq %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xff,0xe6,0xea] vcvtpd2dq %ymm2, %xmm5 -// CHECK: vcvtpd2dqy %ymm2, %xmm1 +// CHECK: vcvtpd2dq %ymm2, %xmm1 // CHECK: encoding: [0xc5,0xff,0xe6,0xca] vcvtpd2dqy %ymm2, %xmm1 diff --git a/test/MC/X86/x86_64-avx-encoding.s b/test/MC/X86/x86_64-avx-encoding.s index 1440d080ee8..b9367d9d1f6 100644 --- a/test/MC/X86/x86_64-avx-encoding.s +++ b/test/MC/X86/x86_64-avx-encoding.s @@ -3368,7 +3368,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3] vcvttpd2dq %xmm11, %xmm10 -// CHECK: vcvttpd2dqy %ymm12, %xmm10 +// CHECK: vcvttpd2dq %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7d,0xe6,0xd4] vcvttpd2dq %ymm12, %xmm10 @@ -3380,7 +3380,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x79,0xe6,0x18] vcvttpd2dqx (%rax), %xmm11 -// CHECK: vcvttpd2dqy %ymm12, %xmm11 +// CHECK: vcvttpd2dq %ymm12, %xmm11 // CHECK: encoding: [0xc4,0x41,0x7d,0xe6,0xdc] vcvttpd2dqy %ymm12, %xmm11 @@ -3388,7 +3388,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x7d,0xe6,0x18] vcvttpd2dqy (%rax), %xmm11 -// CHECK: vcvtpd2psy %ymm12, %xmm10 +// CHECK: vcvtpd2ps %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7d,0x5a,0xd4] vcvtpd2ps %ymm12, %xmm10 @@ -3400,7 +3400,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x79,0x5a,0x18] vcvtpd2psx (%rax), %xmm11 -// CHECK: vcvtpd2psy %ymm12, %xmm11 +// CHECK: vcvtpd2ps %ymm12, %xmm11 // CHECK: encoding: [0xc4,0x41,0x7d,0x5a,0xdc] vcvtpd2psy %ymm12, %xmm11 @@ -3408,11 +3408,11 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x7d,0x5a,0x18] vcvtpd2psy (%rax), %xmm11 -// CHECK: vcvtpd2dqy %ymm12, %xmm10 +// CHECK: vcvtpd2dq %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7f,0xe6,0xd4] vcvtpd2dq %ymm12, %xmm10 -// CHECK: vcvtpd2dqy %ymm12, %xmm11 +// CHECK: vcvtpd2dq %ymm12, %xmm11 // CHECK: encoding: [0xc4,0x41,0x7f,0xe6,0xdc] vcvtpd2dqy %ymm12, %xmm11 -- 2.50.1