From 450118fdf806a6411f9454424915f662fd3f6e88 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Wed, 27 Feb 2019 20:29:25 +0800 Subject: [PATCH] =?utf8?q?soc/rtc=5Fclk:=20don=E2=80=99t=20clear=20DPORT?= =?utf8?q?=5FCPUPERIOD=5FSEL=20when=20switching=20to=20XTAL?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This is not necessary since RTC_CNTL_SOC_CLK_SEL is set before this. --- components/soc/esp32/rtc_clk.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 07fc1c5d60..5fe05464c4 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -400,7 +400,6 @@ static void rtc_clk_cpu_freq_to_xtal() REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL); - DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL rtc_clk_apb_freq_update(xtal_freq * MHZ); s_cur_freq = RTC_CPU_FREQ_XTAL; @@ -472,7 +471,6 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) */ rtc_clk_wait_for_slow_cycle(); - DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); -- 2.40.0