From 42cefc173fdd0ac510726330081b16361e3cf0fd Mon Sep 17 00:00:00 2001 From: XiaXiaotian Date: Sat, 28 Oct 2017 10:19:49 +0800 Subject: [PATCH] refractor WiFi clock setting Do not set WiFi clock in PHY initializing function, move it to WiFi start/stop function. --- components/driver/include/driver/periph_ctrl.h | 2 ++ components/driver/periph_ctrl.c | 13 ++++++++++--- components/esp32/clk.c | 4 ++++ components/esp32/lib | 2 +- components/esp32/phy_init.c | 4 ++-- components/soc/esp32/include/soc/dport_reg.h | 6 +++--- 6 files changed, 22 insertions(+), 9 deletions(-) diff --git a/components/driver/include/driver/periph_ctrl.h b/components/driver/include/driver/periph_ctrl.h index 38770a060a..b418100902 100644 --- a/components/driver/include/driver/periph_ctrl.h +++ b/components/driver/include/driver/periph_ctrl.h @@ -49,6 +49,8 @@ typedef enum { PERIPH_SDIO_SLAVE_MODULE, PERIPH_CAN_MODULE, PERIPH_EMAC_MODULE, + PERIPH_RNG_MODULE, + PERIPH_WIFI_MODULE, PERIPH_BT_MODULE, PERIPH_WIFI_BT_COMMON_MODULE, } periph_module_t; diff --git a/components/driver/periph_ctrl.c b/components/driver/periph_ctrl.c index d63206df37..67431a4276 100644 --- a/components/driver/periph_ctrl.c +++ b/components/driver/periph_ctrl.c @@ -106,6 +106,10 @@ static uint32_t get_clk_en_mask(periph_module_t periph) return DPORT_CAN_CLK_EN; case PERIPH_EMAC_MODULE: return DPORT_WIFI_CLK_EMAC_EN; + case PERIPH_RNG_MODULE: + return DPORT_WIFI_CLK_RNG_EN; + case PERIPH_WIFI_MODULE: + return DPORT_WIFI_CLK_WIFI_EN_M; case PERIPH_BT_MODULE: return DPORT_WIFI_CLK_BT_EN_M; case PERIPH_WIFI_BT_COMMON_MODULE: @@ -163,13 +167,14 @@ static uint32_t get_rst_en_mask(periph_module_t periph) case PERIPH_SPI_DMA_MODULE: return DPORT_SPI_DMA_RST; case PERIPH_SDMMC_MODULE: - return DPORT_WIFI_CLK_SDIO_HOST_EN; + return DPORT_SDIO_HOST_RST; case PERIPH_SDIO_SLAVE_MODULE: - return DPORT_WIFI_CLK_SDIOSLAVE_EN; + return DPORT_SDIO_RST; case PERIPH_CAN_MODULE: return DPORT_CAN_RST; case PERIPH_EMAC_MODULE: - return DPORT_WIFI_CLK_EMAC_EN; + return DPORT_EMAC_RST; + case PERIPH_WIFI_MODULE: case PERIPH_BT_MODULE: case PERIPH_WIFI_BT_COMMON_MODULE: return 0; @@ -186,6 +191,8 @@ static bool is_wifi_clk_peripheral(periph_module_t periph) case PERIPH_SDMMC_MODULE: case PERIPH_SDIO_SLAVE_MODULE: case PERIPH_EMAC_MODULE: + case PERIPH_RNG_MODULE: + case PERIPH_WIFI_MODULE: case PERIPH_BT_MODULE: case PERIPH_WIFI_BT_COMMON_MODULE: return true; diff --git a/components/esp32/clk.c b/components/esp32/clk.c index 6e01cc2ea1..34b36b9bb8 100644 --- a/components/esp32/clk.c +++ b/components/esp32/clk.c @@ -29,6 +29,7 @@ #include "soc/rtc_cntl_reg.h" #include "soc/dport_reg.h" #include "soc/i2s_reg.h" +#include "driver/periph_ctrl.h" #include "xtensa/core-macros.h" /* Number of cycles to wait from the 32k XTAL oscillator to consider it running. @@ -236,4 +237,7 @@ void esp_perip_clk_init(void) /* Disable WiFi/BT/SDIO clocks. */ DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk); + + /* Enable RNG clock. */ + periph_module_enable(PERIPH_RNG_MODULE); } diff --git a/components/esp32/lib b/components/esp32/lib index 4d59fe9623..f5733f50ce 160000 --- a/components/esp32/lib +++ b/components/esp32/lib @@ -1 +1 @@ -Subproject commit 4d59fe9623f5a7cab7ef4b0b4cda1772d4795631 +Subproject commit f5733f50ce43bf54d18328499f3cf8cf61c7087d diff --git a/components/esp32/phy_init.c b/components/esp32/phy_init.c index ac114e9504..94a89afd67 100644 --- a/components/esp32/phy_init.c +++ b/components/esp32/phy_init.c @@ -51,7 +51,7 @@ esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data, _lock_acquire(&s_phy_rf_init_lock); if (s_phy_rf_init_count == 0) { - // Enable WiFi peripheral clock + // Enable WiFi/BT common peripheral clock periph_module_enable(PERIPH_WIFI_BT_COMMON_MODULE); ESP_LOGV(TAG, "register_chipv7_phy, init_data=%p, cal_data=%p, mode=%d", init_data, calibration_data, mode); @@ -76,7 +76,7 @@ esp_err_t esp_phy_rf_deinit(void) if (s_phy_rf_init_count == 1) { // Disable PHY and RF. phy_close_rf(); - // Disable WiFi peripheral clock. Do not disable clock for hardware RNG + // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware RNG periph_module_disable(PERIPH_WIFI_BT_COMMON_MODULE); } else { #if CONFIG_SW_COEXIST_ENABLE diff --git a/components/soc/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h index 3c2ae160d3..b7c9bdb905 100644 --- a/components/soc/esp32/include/soc/dport_reg.h +++ b/components/soc/esp32/include/soc/dport_reg.h @@ -1043,10 +1043,10 @@ #define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF #define DPORT_WIFI_CLK_EN_S 0 -/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15 */ -#define DPORT_WIFI_CLK_WIFI_EN 0x000007cf +/* Mask for all Wifi clock bits - 1, 2, 10 */ +#define DPORT_WIFI_CLK_WIFI_EN 0x00000406 #define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S)) -#define DPORT_WIFI_CLK_WIFI_EN_V 0x1FF +#define DPORT_WIFI_CLK_WIFI_EN_V 0x406 #define DPORT_WIFI_CLK_WIFI_EN_S 0 /* Mask for all Bluetooth clock bits - 11, 16, 17 */ #define DPORT_WIFI_CLK_BT_EN 0x61 -- 2.40.0