From 42988461bb266eb0359f136417498b44a9f786b6 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Mon, 23 Jun 2014 20:28:43 +0000 Subject: [PATCH] Fix spelling. s/overloaed/overloaded/ git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@211530 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/CGBuiltin.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp index d9d1fd1041..a177fd71c7 100644 --- a/lib/CodeGen/CGBuiltin.cpp +++ b/lib/CodeGen/CGBuiltin.cpp @@ -3762,7 +3762,7 @@ Value *CodeGenFunction:: emitVectorWrappedScalar8Intrinsic(unsigned Int, SmallVectorImpl &Ops, const char *Name) { // i8 is not a legal types for AArch64, so we can't just use - // a normal overloaed intrinsic call for these scalar types. Instead + // a normal overloaded intrinsic call for these scalar types. Instead // we'll build 64-bit vectors w/ lane zero being our input values and // perform the operation on that. The back end can pattern match directly // to the scalar instruction. @@ -3778,7 +3778,7 @@ Value *CodeGenFunction:: emitVectorWrappedScalar16Intrinsic(unsigned Int, SmallVectorImpl &Ops, const char *Name) { // i16 is not a legal types for AArch64, so we can't just use - // a normal overloaed intrinsic call for these scalar types. Instead + // a normal overloaded intrinsic call for these scalar types. Instead // we'll build 64-bit vectors w/ lane zero being our input values and // perform the operation on that. The back end can pattern match directly // to the scalar instruction. -- 2.40.0