From 428e69317e7a7875d204a6228b12d6c70db7fc9f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 30 Mar 2017 12:59:53 +0000 Subject: [PATCH] Spelling mistakes in comments. NFCI. Based on corrections mentioned in patch for clang for PR27635 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299072 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineFunctionInitializer.h | 2 +- include/llvm/Support/FormatVariadic.h | 2 +- lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- lib/CodeGen/DetectDeadLanes.cpp | 2 +- lib/Target/Mips/MipsHazardSchedule.cpp | 2 +- lib/Target/NVPTX/NVPTXISelLowering.cpp | 2 +- lib/Target/PowerPC/PPCInstrVSX.td | 2 +- lib/Target/X86/X86InstrCompiler.td | 4 ++-- lib/Transforms/InstCombine/InstCombineCalls.cpp | 2 +- lib/XRay/Trace.cpp | 2 +- tools/dsymutil/DwarfLinker.cpp | 6 +++--- tools/dsymutil/MachOUtils.cpp | 2 +- tools/llvm-c-test/echo.cpp | 2 +- tools/lto/lto.cpp | 2 +- 14 files changed, 17 insertions(+), 17 deletions(-) diff --git a/include/llvm/CodeGen/MachineFunctionInitializer.h b/include/llvm/CodeGen/MachineFunctionInitializer.h index ff4c29cc014..c644c9783e2 100644 --- a/include/llvm/CodeGen/MachineFunctionInitializer.h +++ b/include/llvm/CodeGen/MachineFunctionInitializer.h @@ -1,4 +1,4 @@ -//===- MachineFunctionInitalizer.h - machine function initializer ---------===// +//===- MachineFunctionInitializer.h - machine function initializer ---------===// // // The LLVM Compiler Infrastructure // diff --git a/include/llvm/Support/FormatVariadic.h b/include/llvm/Support/FormatVariadic.h index e5f5c9615cb..3a4668687cc 100644 --- a/include/llvm/Support/FormatVariadic.h +++ b/include/llvm/Support/FormatVariadic.h @@ -196,7 +196,7 @@ public: // "}}" to print a literal '}'. // // ===Parameter Indexing=== -// `index` specifies the index of the paramter in the parameter pack to format +// `index` specifies the index of the parameter in the parameter pack to format // into the output. Note that it is possible to refer to the same parameter // index multiple times in a given format string. This makes it possible to // output the same value multiple times without passing it multiple times to the diff --git a/lib/Bitcode/Reader/MetadataLoader.cpp b/lib/Bitcode/Reader/MetadataLoader.cpp index 499dd118a22..274dfe89cce 100644 --- a/lib/Bitcode/Reader/MetadataLoader.cpp +++ b/lib/Bitcode/Reader/MetadataLoader.cpp @@ -1495,7 +1495,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( bool HasAlignment = Record[0] & 2; // 2nd field used to be an artificial tag, either DW_TAG_auto_variable or // DW_TAG_arg_variable, if we have alignment flag encoded it means, that - // this is newer version of record which doesn't have artifical tag. + // this is newer version of record which doesn't have artificial tag. bool HasTag = !HasAlignment && Record.size() > 8; DINode::DIFlags Flags = static_cast(Record[7 + HasTag]); uint32_t AlignInBits = 0; diff --git a/lib/CodeGen/DetectDeadLanes.cpp b/lib/CodeGen/DetectDeadLanes.cpp index a7ba694c144..6f4ea1912cf 100644 --- a/lib/CodeGen/DetectDeadLanes.cpp +++ b/lib/CodeGen/DetectDeadLanes.cpp @@ -441,7 +441,7 @@ LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) { const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); if (CrossCopy) - DEBUG(dbgs() << "Copy accross incompatible classes: " << UseMI); + DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI); } if (!CrossCopy) diff --git a/lib/Target/Mips/MipsHazardSchedule.cpp b/lib/Target/Mips/MipsHazardSchedule.cpp index 31b86124bc8..87446e38aca 100644 --- a/lib/Target/Mips/MipsHazardSchedule.cpp +++ b/lib/Target/Mips/MipsHazardSchedule.cpp @@ -36,7 +36,7 @@ /// /// A) A previous pass has created a compact branch directly. /// B) Transforming a delay slot branch into compact branch. This case can be -/// difficult to process as lookahead for hazards is insufficent, as +/// difficult to process as lookahead for hazards is insufficient, as /// backwards delay slot fillling can also produce hazards in previously /// processed instuctions. /// diff --git a/lib/Target/NVPTX/NVPTXISelLowering.cpp b/lib/Target/NVPTX/NVPTXISelLowering.cpp index 69a210f1a91..36e4382777c 100644 --- a/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -1556,7 +1556,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } ++OIdx; } - assert(StoreOperands.empty() && "Unfinished paramter store."); + assert(StoreOperands.empty() && "Unfinished parameter store."); if (VTs.size() > 0) --OIdx; ++paramCount; diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td index d7b3081c410..13603732397 100644 --- a/lib/Target/PowerPC/PPCInstrVSX.td +++ b/lib/Target/PowerPC/PPCInstrVSX.td @@ -2198,7 +2198,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { } // UseVSXReg = 1 // Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a - // seperate pattern so that it can convert the input register class from + // separate pattern so that it can convert the input register class from // VRRC(v8i16) to VSRC. def : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)), (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>; diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index e7f6492bb00..e592c2b3c0a 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -772,11 +772,11 @@ defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", // the pseudo. The argument feeding EBX is ebx_input. // // The additional argument, $ebx_save, is a temporary register used to -// save the value of RBX accross the actual instruction. +// save the value of RBX across the actual instruction. // // To make sure the register assigned to $ebx_save does not interfere with // the definition of the actual instruction, we use a definition $dst which -// is tied to $rbx_save. That way, the live-range of $rbx_save spans accross +// is tied to $rbx_save. That way, the live-range of $rbx_save spans across // the instruction and we are sure we will have a valid register to restore // the value of RBX. let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX], diff --git a/lib/Transforms/InstCombine/InstCombineCalls.cpp b/lib/Transforms/InstCombine/InstCombineCalls.cpp index 845cf109897..f3fc1e2d631 100644 --- a/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -3623,7 +3623,7 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) { m_Intrinsic(m_Value(NextCond)))) { Value *CurrCond = II->getArgOperand(0); - // Remove a guard that it is immediately preceeded by an identical guard. + // Remove a guard that it is immediately preceded by an identical guard. if (CurrCond == NextCond) return eraseInstFromFunction(*NextInst); diff --git a/lib/XRay/Trace.cpp b/lib/XRay/Trace.cpp index 5f64a5da144..90be4a91602 100644 --- a/lib/XRay/Trace.cpp +++ b/lib/XRay/Trace.cpp @@ -332,7 +332,7 @@ Error processFDRFunctionRecord(FDRState &State, uint8_t RecordFirstByte, /// The following is an attempt to document the grammar of the format, which is /// parsed by this function for little-endian machines. Since the format makes /// use of BitFields, when we support big-Endian architectures, we will need to -/// adjust not only the endianess parameter to llvm's RecordExtractor, but also +/// adjust not only the endianness parameter to llvm's RecordExtractor, but also /// the bit twiddling logic, which is consistent with the little-endian /// convention that BitFields within a struct will first be packed into the /// least significant bits the address they belong to. diff --git a/tools/dsymutil/DwarfLinker.cpp b/tools/dsymutil/DwarfLinker.cpp index 35cefaa69e8..25f1a0f2712 100644 --- a/tools/dsymutil/DwarfLinker.cpp +++ b/tools/dsymutil/DwarfLinker.cpp @@ -363,7 +363,7 @@ private: Optional UnitRangeAttribute; /// @} - /// \brief Location attributes that need to be transfered from th + /// \brief Location attributes that need to be transferred from the /// original debug_loc section to the liked one. They are stored /// along with the PC offset that is to be applied to their /// function's address. @@ -1084,7 +1084,7 @@ void DwarfStreamer::emitCIE(StringRef CIEBytes) { /// \brief Emit a FDE into the debug_frame section. \p FDEBytes /// contains the FDE data without the length, CIE offset and address -/// which will be replaced with the paramter values. +/// which will be replaced with the parameter values. void DwarfStreamer::emitFDE(uint32_t CIEOffset, uint32_t AddrSize, uint32_t Address, StringRef FDEBytes) { MS->SwitchSection(MC->getObjectFileInfo()->getDwarfFrameSection()); @@ -3071,7 +3071,7 @@ void DwarfLinker::patchLineTableForUnit(CompileUnit &Unit, if (LineTable.Prologue.Version != 2 || LineTable.Prologue.DefaultIsStmt != DWARF2_LINE_DEFAULT_IS_STMT || LineTable.Prologue.OpcodeBase > 13) - reportWarning("line table paramters mismatch. Cannot emit."); + reportWarning("line table parameters mismatch. Cannot emit."); else { MCDwarfLineTableParams Params; Params.DWARF2LineOpcodeBase = LineTable.Prologue.OpcodeBase; diff --git a/tools/dsymutil/MachOUtils.cpp b/tools/dsymutil/MachOUtils.cpp index c1422f6eaab..ea6f113e4fa 100644 --- a/tools/dsymutil/MachOUtils.cpp +++ b/tools/dsymutil/MachOUtils.cpp @@ -220,7 +220,7 @@ getSection(const object::MachOObjectFile &Obj, // The function also tries to find a hole in the address map to fit the __DWARF // segment of \a DwarfSegmentSize size. \a EndAddress is updated to point at the // highest segment address. -// When the __LINKEDIT segment is transfered, its offset and size are set resp. +// When the __LINKEDIT segment is transferred, its offset and size are set resp. // to \a LinkeditOffset and \a LinkeditSize. template static void transferSegmentAndSections( diff --git a/tools/llvm-c-test/echo.cpp b/tools/llvm-c-test/echo.cpp index 72ff138c74e..52ce85c5778 100644 --- a/tools/llvm-c-test/echo.cpp +++ b/tools/llvm-c-test/echo.cpp @@ -591,7 +591,7 @@ struct FunCloner { break; } case LLVMPHI: { - // We need to agressively set things here because of loops. + // We need to aggressively set things here because of loops. VMap[Src] = Dst = LLVMBuildPhi(Builder, CloneType(Src), Name); SmallVector Values; diff --git a/tools/lto/lto.cpp b/tools/lto/lto.cpp index e28c7aaf526..1b218a64cbf 100644 --- a/tools/lto/lto.cpp +++ b/tools/lto/lto.cpp @@ -272,7 +272,7 @@ lto_module_t lto_module_create_in_local_context(const void *mem, size_t length, lto_initialize(); llvm::TargetOptions Options = InitTargetOptionsFromCodeGenFlags(); - // Create a local context. Ownership will be transfered to LTOModule. + // Create a local context. Ownership will be transferred to LTOModule. std::unique_ptr Context = llvm::make_unique(); Context->setDiagnosticHandler(diagnosticHandler, nullptr, true); -- 2.40.0