From 4247581cf2689ad987fa74899ed14ac1a94ec18e Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Thu, 3 Aug 2017 15:41:26 +0000 Subject: [PATCH] Revert r309923, it caused PR34045. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309950 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 166 ++---------------------- lib/Target/ARM/ARMISelLowering.h | 3 +- test/CodeGen/ARM/intrinsics-overflow.ll | 88 +++---------- 3 files changed, 28 insertions(+), 229 deletions(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 7156d683a2e..9746490988e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -801,9 +801,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SSUBO, MVT::i32, Custom); setOperationAction(ISD::USUBO, MVT::i32, Custom); - setOperationAction(ISD::ADDCARRY, MVT::i32, Custom); - setOperationAction(ISD::SUBCARRY, MVT::i32, Custom); - // i64 operation support. setOperationAction(ISD::MUL, MVT::i64, Expand); setOperationAction(ISD::MULHU, MVT::i32, Expand); @@ -3955,7 +3952,7 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG, } SDValue -ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const { +ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { // Let legalize expand this if it isn't a legal type yet. if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType())) return SDValue(); @@ -3977,66 +3974,6 @@ ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); } -static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry, - SelectionDAG &DAG) { - SDLoc DL(BoolCarry); - EVT CarryVT = BoolCarry.getValueType(); - - APInt NegOne = APInt::getAllOnesValue(CarryVT.getScalarSizeInBits()); - // This converts the boolean value carry into the carry flag by doing - // ARMISD::ADDC Carry, ~0 - return DAG.getNode(ARMISD::ADDC, DL, DAG.getVTList(CarryVT, MVT::i32), - BoolCarry, DAG.getConstant(NegOne, DL, CarryVT)); -} - -static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT, - SelectionDAG &DAG) { - SDLoc DL(Flags); - - // Now convert the carry flag into a boolean carry. We do this - // using ARMISD:ADDE 0, 0, Carry - return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), - DAG.getConstant(0, DL, MVT::i32), - DAG.getConstant(0, DL, MVT::i32), Flags); -} - -SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op, - SelectionDAG &DAG) const { - // Let legalize expand this if it isn't a legal type yet. - if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType())) - return SDValue(); - - SDValue LHS = Op.getOperand(0); - SDValue RHS = Op.getOperand(1); - SDLoc dl(Op); - - EVT VT = Op.getValueType(); - SDVTList VTs = DAG.getVTList(VT, MVT::i32); - SDValue Value; - SDValue Overflow; - switch (Op.getOpcode()) { - default: - llvm_unreachable("Unknown overflow instruction!"); - case ISD::UADDO: - Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS); - // Convert the carry flag into a boolean value. - Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG); - break; - case ISD::USUBO: { - Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS); - // Convert the carry flag into a boolean value. - Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG); - // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow - // value. So compute 1 - C. - Overflow = DAG.getNode(ISD::SUB, dl, VTs, - DAG.getConstant(1, dl, MVT::i32), Overflow); - break; - } - } - - return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); -} - SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { SDValue Cond = Op.getOperand(0); SDValue SelectTrue = Op.getOperand(1); @@ -7441,53 +7378,6 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { Op.getOperand(1), Op.getOperand(2)); } -static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) { - SDNode *N = Op.getNode(); - EVT VT = N->getValueType(0); - SDVTList VTs = DAG.getVTList(VT, MVT::i32); - - SDValue Carry = Op.getOperand(2); - EVT CarryVT = Carry.getValueType(); - - SDLoc DL(Op); - - APInt NegOne = APInt::getAllOnesValue(CarryVT.getScalarSizeInBits()); - - SDValue Result; - if (Op.getOpcode() == ISD::ADDCARRY) { - // This converts the boolean value carry into the carry flag. - Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG); - - // Do the addition proper using the carry flag we wanted. - Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0), - Op.getOperand(1), Carry.getValue(1)); - - // Now convert the carry flag into a boolean value. - Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG); - } else { - // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we - // have to invert the carry first. - Carry = - DAG.getNode(ISD::SUB, DL, VTs, DAG.getConstant(1, DL, MVT::i32), Carry); - // This converts the boolean value carry into the carry flag. - Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG); - - // Do the subtraction proper using the carry flag we wanted. - Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0), - Op.getOperand(1), Carry.getValue(1)); - - // Now convert the carry flag into a boolean value. - Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG); - // But the carry returned by ARMISD::SUBE is not a borrow as expected - // by ISD::SUBCARRY, so compute 1 - C. - Carry = - DAG.getNode(ISD::SUB, DL, VTs, DAG.getConstant(1, DL, MVT::i32), Carry); - } - - // Return both values. - return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry); -} - SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const { assert(Subtarget->isTargetDarwin()); @@ -7842,14 +7732,11 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::ADDE: case ISD::SUBC: case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); - case ISD::ADDCARRY: - case ISD::SUBCARRY: return LowerADDSUBCARRY(Op, DAG); case ISD::SADDO: - case ISD::SSUBO: - return LowerSignedALUO(Op, DAG); case ISD::UADDO: + case ISD::SSUBO: case ISD::USUBO: - return LowerUnsignedALUO(Op, DAG); + return LowerXALUO(Op, DAG); case ISD::ATOMIC_LOAD: case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); @@ -9984,22 +9871,8 @@ static SDValue PerformUMLALCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); } -static SDValue PerformAddcSubcCombine(SDNode *N, - TargetLowering::DAGCombinerInfo &DCI, +static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) { - SelectionDAG &DAG(DCI.DAG); - - if (N->getOpcode() == ARMISD::ADDC) { - // (ADDC (ADDE 0, 0, C), -1) -> C - SDValue LHS = N->getOperand(0); - SDValue RHS = N->getOperand(1); - if (LHS->getOpcode() == ARMISD::ADDE && - isNullConstant(LHS->getOperand(0)) && - isNullConstant(LHS->getOperand(1)) && isAllOnesConstant(RHS)) { - return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2)); - } - } - if (Subtarget->isThumb1Only()) { SDValue RHS = N->getOperand(1); if (ConstantSDNode *C = dyn_cast(RHS)) { @@ -11888,14 +11761,6 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); } -static const APInt *isPowerOf2Constant(SDValue V) { - ConstantSDNode *C = dyn_cast(V); - if (!C) - return nullptr; - const APInt *CV = &C->getAPIntValue(); - return CV->isPowerOf2() ? CV : nullptr; -} - SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const { // If we have a CMOV, OR and AND combination such as: // if (x & CN) @@ -11924,8 +11789,8 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D SDValue And = CmpZ->getOperand(0); if (And->getOpcode() != ISD::AND) return SDValue(); - const APInt *AndC = isPowerOf2Constant(And->getOperand(1)); - if (!AndC) + ConstantSDNode *AndC = dyn_cast(And->getOperand(1)); + if (!AndC || !AndC->getAPIntValue().isPowerOf2()) return SDValue(); SDValue X = And->getOperand(0); @@ -11965,7 +11830,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D SDValue V = Y; SDLoc dl(X); EVT VT = X.getValueType(); - unsigned BitInX = AndC->logBase2(); + unsigned BitInX = AndC->getAPIntValue().logBase2(); if (BitInX != 0) { // We must shift X first. @@ -12126,7 +11991,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget); case ISD::AND: return PerformANDCombine(N, DCI, Subtarget); case ARMISD::ADDC: - case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget); + case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI.DAG, Subtarget); case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI.DAG, Subtarget); case ARMISD::BFI: return PerformBFICombine(N, DCI); case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget); @@ -12800,17 +12665,10 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, case ARMISD::ADDE: case ARMISD::SUBC: case ARMISD::SUBE: - // Special cases when we convert a carry to a boolean. - if (Op.getResNo() == 0) { - SDValue LHS = Op.getOperand(0); - SDValue RHS = Op.getOperand(1); - // (ADDE 0, 0, C) will give us a single bit. - if (Op->getOpcode() == ARMISD::ADDE && isNullConstant(LHS) && - isNullConstant(RHS)) { - Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); - return; - } - } + // These nodes' second result is a boolean + if (Op.getResNo() == 0) + break; + Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); break; case ARMISD::CMOV: { // Bits are known zero/one if known on the LHS and RHS. diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 39e54c18c03..6ccd4b87000 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -618,8 +618,7 @@ class InstrItineraryData; SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; diff --git a/test/CodeGen/ARM/intrinsics-overflow.ll b/test/CodeGen/ARM/intrinsics-overflow.ll index af555d2240c..af3dd9dd411 100644 --- a/test/CodeGen/ARM/intrinsics-overflow.ll +++ b/test/CodeGen/ARM/intrinsics-overflow.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -mtriple=arm-linux -mcpu=generic -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV6 -; RUN: llc < %s -mtriple=thumbv7-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV7 +; RUN: llc < %s -mtriple=arm-linux -mcpu=generic | FileCheck %s define i32 @uadd_overflow(i32 %a, i32 %b) #0 { %sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) @@ -9,19 +7,10 @@ define i32 @uadd_overflow(i32 %a, i32 %b) #0 { ret i32 %2 ; CHECK-LABEL: uadd_overflow: - - ; ARM: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] - ; ARM: mov r[[R2:[0-9]+]], #0 - ; ARM: adc r[[R0]], r[[R2]], #0 - - ; THUMBV6: movs r[[R2:[0-9]+]], #0 - ; THUMBV6: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] - ; THUMBV6: adcs r[[R2]], r[[R2]] - ; THUMBV6: mov r[[R0]], r[[R2]] - - ; THUMBV7: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] - ; THUMBV7: mov.w r[[R2:[0-9]+]], #0 - ; THUMBV7: adc r[[R0]], r[[R2]], #0 + ; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] + ; CHECK: mov r[[R1]], #1 + ; CHECK: cmp r[[R2]], r[[R0]] + ; CHECK: movhs r[[R1]], #0 } @@ -32,26 +21,10 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 { ret i32 %2 ; CHECK-LABEL: sadd_overflow: - - ; ARM: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] - ; ARM: mov r[[R1]], #1 - ; ARM: cmp r[[R2]], r[[R0]] - ; ARM: movvc r[[R1]], #0 - - ; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]] - ; THUMBV6: adds r[[R3:[0-9]+]], r[[R2]], r[[R1:[0-9]+]] - ; THUMBV6: movs r[[R0]], #0 - ; THUMBV6: movs r[[R1]], #1 - ; THUMBV6: cmp r[[R3]], r[[R2]] - ; THUMBV6: bvc .L[[LABEL:.*]] - ; THUMBV6: mov r[[R0]], r[[R1]] - ; THUMBV6: .L[[LABEL]]: - - ; THUMBV7: movs r[[R1]], #1 - ; THUMBV7: cmp r[[R2]], r[[R0]] - ; THUMBV7: it vc - ; THUMBV7: movvc r[[R1]], #0 - ; THUMBV7: mov r[[R0]], r[[R1]] + ; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] + ; CHECK: mov r[[R1]], #1 + ; CHECK: cmp r[[R2]], r[[R0]] + ; CHECK: movvc r[[R1]], #0 } define i32 @usub_overflow(i32 %a, i32 %b) #0 { @@ -61,26 +34,9 @@ define i32 @usub_overflow(i32 %a, i32 %b) #0 { ret i32 %2 ; CHECK-LABEL: usub_overflow: - - ; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] - ; ARM: mov r[[R2:[0-9]+]], #0 - ; ARM: adc r[[R0]], r[[R2]], #0 - ; ARM: rsb r[[R0]], r[[R0]], #1 - - ; THUMBV6: movs r[[R2:[0-9]+]], #0 - ; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] - ; THUMBV6: adcs r[[R2]], r[[R2]] - ; THUMBV6: movs r[[R0]], #1 - ; THUMBV6: subs r[[R0]], r[[R0]], r[[R2]] - - ; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] - ; THUMBV7: mov.w r[[R2:[0-9]+]], #0 - ; THUMBV7: adc r[[R0]], r[[R2]], #0 - ; THUMBV7: rsb.w r[[R0]], r[[R0]], #1 - - ; We should know that the overflow is just 1 bit, - ; no need to clear any other bit - ; CHECK-NOT: and + ; CHECK: mov r[[R2]], #1 + ; CHECK: cmp r[[R0]], r[[R1]] + ; CHECK: movhs r[[R2]], #0 } define i32 @ssub_overflow(i32 %a, i32 %b) #0 { @@ -90,23 +46,9 @@ define i32 @ssub_overflow(i32 %a, i32 %b) #0 { ret i32 %2 ; CHECK-LABEL: ssub_overflow: - - ; ARM: mov r[[R2]], #1 - ; ARM: cmp r[[R0]], r[[R1]] - ; ARM: movvc r[[R2]], #0 - - ; THUMBV6: movs r[[R0]], #0 - ; THUMBV6: movs r[[R3:[0-9]+]], #1 - ; THUMBV6: cmp r[[R2]], r[[R1:[0-9]+]] - ; THUMBV6: bvc .L[[LABEL:.*]] - ; THUMBV6: mov r[[R0]], r[[R3]] - ; THUMBV6: .L[[LABEL]]: - - ; THUMBV7: movs r[[R2:[0-9]+]], #1 - ; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]] - ; THUMBV7: it vc - ; THUMBV7: movvc r[[R2]], #0 - ; THUMBV7: mov r[[R0]], r[[R2]] + ; CHECK: mov r[[R2]], #1 + ; CHECK: cmp r[[R0]], r[[R1]] + ; CHECK: movvc r[[R2]], #0 } declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1 -- 2.50.1