From 41f9733d3d3e5edf7a1053604772e2c4ca0a6e4b Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 20 Jun 2019 14:59:28 +0000 Subject: [PATCH] Virtualize TargetInstrInfo::getRegClass() AMDGPU target needs to override getRegClass() used during instruction selection. We now may have either 32 or 64 bit conditional registers used in the same instructions. For that purpose special SReg_1 register class is created which is dynamically resolved to either SReg_64 or SGPR_32 depending on the subtarget attributes. Differential Revision: https://reviews.llvm.org/D63205 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363931 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/TargetInstrInfo.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/llvm/CodeGen/TargetInstrInfo.h b/include/llvm/CodeGen/TargetInstrInfo.h index 20c4934c7d5..25b04f8c019 100644 --- a/include/llvm/CodeGen/TargetInstrInfo.h +++ b/include/llvm/CodeGen/TargetInstrInfo.h @@ -81,6 +81,7 @@ public: /// Given a machine instruction descriptor, returns the register /// class constraint for OpNum, or NULL. + virtual const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const; -- 2.50.1