From 3f22f87fb522a96395699a9cb6d7d7eb73724921 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 3 Oct 2016 22:43:53 +0000 Subject: [PATCH] [WebAssembly] Update to more stack-machine-oriented terminology. WebAssembly has officially switched from being an AST to being a stack machine. Update various bits of terminology and README.md entries accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283154 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/WebAssembly/README.txt | 18 ++++++++++----- .../WebAssembly/WebAssemblyCFGStackify.cpp | 2 +- .../WebAssembly/WebAssemblyInstrControl.td | 6 ++--- .../WebAssembly/WebAssemblyLowerBrUnless.cpp | 2 +- .../WebAssembly/WebAssemblyRegStackify.cpp | 22 +++++++++---------- .../WebAssembly/WebAssemblyRegisterInfo.td | 6 ++--- .../WebAssemblyReplacePhysRegs.cpp | 2 +- .../WebAssembly/WebAssemblyTargetMachine.cpp | 6 ++--- 8 files changed, 36 insertions(+), 28 deletions(-) diff --git a/lib/Target/WebAssembly/README.txt b/lib/Target/WebAssembly/README.txt index 4a0fa0badfb..486b587fb74 100644 --- a/lib/Target/WebAssembly/README.txt +++ b/lib/Target/WebAssembly/README.txt @@ -24,13 +24,13 @@ test suite. The tests can be run locally using: //===---------------------------------------------------------------------===// -Br, br_if, and br_table instructions can support having a value on the -expression stack across the jump (sometimes). We should (a) model this, and -(b) extend the stackifier to utilize it. +Br, br_if, and br_table instructions can support having a value on the value +stack across the jump (sometimes). We should (a) model this, and (b) extend +the stackifier to utilize it. //===---------------------------------------------------------------------===// -The min/max operators aren't exactly a(); auto &MDT = getAnalysis(); - // Liveness is not tracked for EXPR_STACK physreg. + // Liveness is not tracked for VALUE_STACK physreg. const auto &TII = *MF.getSubtarget().getInstrInfo(); WebAssemblyFunctionInfo &MFI = *MF.getInfo(); MF.getRegInfo().invalidateLiveness(); diff --git a/lib/Target/WebAssembly/WebAssemblyInstrControl.td b/lib/Target/WebAssembly/WebAssemblyInstrControl.td index e357af63bae..a3e7f012089 100644 --- a/lib/Target/WebAssembly/WebAssemblyInstrControl.td +++ b/lib/Target/WebAssembly/WebAssemblyInstrControl.td @@ -59,14 +59,14 @@ def BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops), } // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 // Placemarkers to indicate the start or end of a block or loop scope. These -// use/clobber EXPR_STACK to prevent them from being moved into the middle of +// use/clobber VALUE_STACK to prevent them from being moved into the middle of // an expression tree. -let Uses = [EXPR_STACK], Defs = [EXPR_STACK] in { +let Uses = [VALUE_STACK], Defs = [VALUE_STACK] in { def BLOCK : I<(outs), (ins), [], "block">; def LOOP : I<(outs), (ins), [], "loop">; def END_BLOCK : I<(outs), (ins), [], "end_block">; def END_LOOP : I<(outs), (ins), [], "end_loop">; -} // Uses = [EXPR_STACK], Defs = [EXPR_STACK] +} // Uses = [VALUE_STACK], Defs = [VALUE_STACK] multiclass RETURN { def RETURN_#vt : I<(outs), (ins vt:$val), [(WebAssemblyreturn vt:$val)], diff --git a/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp b/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp index f3bfa5506e4..150ec5d65b3 100644 --- a/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp +++ b/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp @@ -104,7 +104,7 @@ bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) { } // If we weren't able to invert the condition in place. Insert an - // expression to invert it. + // instruction to invert it. if (!Inverted) { unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass); MFI.stackifyVReg(Tmp); diff --git a/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index 1b717658efb..6de724cfbdf 100644 --- a/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -13,10 +13,10 @@ /// This pass reorders instructions to put register uses and defs in an order /// such that they form single-use expression trees. Registers fitting this form /// are then marked as "stackified", meaning references to them are replaced by -/// "push" and "pop" from the stack. +/// "push" and "pop" from the value stack. /// /// This is primarily a code size optimization, since temporary values on the -/// expression don't need to be named. +/// value stack don't need to be named. /// //===----------------------------------------------------------------------===// @@ -73,15 +73,15 @@ FunctionPass *llvm::createWebAssemblyRegStackify() { // expression stack ordering constraints for an instruction which is on // the expression stack. static void ImposeStackOrdering(MachineInstr *MI) { - // Write the opaque EXPR_STACK register. - if (!MI->definesRegister(WebAssembly::EXPR_STACK)) - MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK, + // Write the opaque VALUE_STACK register. + if (!MI->definesRegister(WebAssembly::VALUE_STACK)) + MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, /*isDef=*/true, /*isImp=*/true)); - // Also read the opaque EXPR_STACK register. - if (!MI->readsRegister(WebAssembly::EXPR_STACK)) - MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK, + // Also read the opaque VALUE_STACK register. + if (!MI->readsRegister(WebAssembly::VALUE_STACK)) + MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, /*isDef=*/false, /*isImp=*/true)); } @@ -813,12 +813,12 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) { } } - // If we used EXPR_STACK anywhere, add it to the live-in sets everywhere so + // If we used VALUE_STACK anywhere, add it to the live-in sets everywhere so // that it never looks like a use-before-def. if (Changed) { - MF.getRegInfo().addLiveIn(WebAssembly::EXPR_STACK); + MF.getRegInfo().addLiveIn(WebAssembly::VALUE_STACK); for (MachineBasicBlock &MBB : MF) - MBB.addLiveIn(WebAssembly::EXPR_STACK); + MBB.addLiveIn(WebAssembly::VALUE_STACK); } #ifndef NDEBUG diff --git a/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td b/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td index 52456aac0b7..90888100be1 100644 --- a/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td +++ b/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td @@ -41,9 +41,9 @@ def F64_0 : WebAssemblyReg<"%f64.0">; def V128_0: WebAssemblyReg<"%v128">; -// The expression stack "register". This is an opaque entity which serves to -// order uses and defs that must remain in LIFO order. -def EXPR_STACK : WebAssemblyReg<"STACK">; +// The value stack "register". This is an opaque entity which serves to order +// uses and defs that must remain in LIFO order. +def VALUE_STACK : WebAssemblyReg<"STACK">; // The incoming arguments "register". This is an opaque entity which serves to // order the ARGUMENT instructions that are emulating live-in registers and diff --git a/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp b/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp index 0c64641609b..9e944df637d 100644 --- a/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp +++ b/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp @@ -76,7 +76,7 @@ bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) { for (unsigned PReg = WebAssembly::NoRegister + 1; PReg < WebAssembly::NUM_TARGET_REGS; ++PReg) { // Skip fake registers that are never used explicitly. - if (PReg == WebAssembly::EXPR_STACK || PReg == WebAssembly::ARGUMENTS) + if (PReg == WebAssembly::VALUE_STACK || PReg == WebAssembly::ARGUMENTS) continue; // Replace explicit uses of the physical register with a virtual register. diff --git a/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index ee60cf3cd1f..524c49d4cc3 100644 --- a/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -73,10 +73,10 @@ WebAssemblyTargetMachine::WebAssemblyTargetMachine( TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), TLOF(make_unique()) { - // WebAssembly type-checks expressions, but a noreturn function with a return + // WebAssembly type-checks instructions, but a noreturn function with a return // type that doesn't match the context will cause a check failure. So we lower // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's - // 'unreachable' expression which is meant for that case. + // 'unreachable' instructions which is meant for that case. this->Options.TrapUnreachable = true; initAsmInfo(); @@ -237,7 +237,7 @@ void WebAssemblyPassConfig::addPreEmitPass() { // Prepare store instructions for register stackifying. addPass(createWebAssemblyStoreResults()); - // Mark registers as representing wasm's expression stack. This is a key + // Mark registers as representing wasm's value stack. This is a key // code-compression technique in WebAssembly. We run this pass (and // StoreResults above) very late, so that it sees as much code as possible, // including code emitted by PEI and expanded by late tail duplication. -- 2.50.0