From 3db62dd7c755c804829468111ae021b1e0b19f10 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 4 Sep 2019 18:59:43 +0000 Subject: [PATCH] [globalisel] Support trivial COPY in GISelKnownBits Summary: Allow GISelKnownBits to look through the trivial case of TargetOpcode::COPY Reviewers: aditya_nandakumar Subscribers: rovka, hiraditya, volkan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67131 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370955 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 13 +++++++++++++ unittests/CodeGen/GlobalISel/KnownBitsTest.cpp | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/lib/CodeGen/GlobalISel/GISelKnownBits.cpp index 057a32fd1d5..72ffd441233 100644 --- a/lib/CodeGen/GlobalISel/GISelKnownBits.cpp +++ b/lib/CodeGen/GlobalISel/GISelKnownBits.cpp @@ -112,6 +112,19 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known, default: TL.computeKnownBitsForTargetInstr(R, Known, DemandedElts, MRI, Depth); break; + case TargetOpcode::COPY: { + MachineOperand Dst = MI.getOperand(0); + MachineOperand Src = MI.getOperand(1); + // Look through trivial copies. + // We can't use NoSubRegister by name as it's defined by each target but + // it's always defined to be 0 by tablegen. + if (Dst.getSubReg() == 0 /*NoSubRegister*/ && Src.getReg().isVirtual() && + Src.getSubReg() == 0 /*NoSubRegister*/) { + // Don't increment Depth for this one since we didn't do any work. + computeKnownBitsImpl(Src.getReg(), Known, DemandedElts, Depth); + } + break; + } case TargetOpcode::G_CONSTANT: { auto CstVal = getConstantVRegVal(R, MRI); Known.One = *CstVal; diff --git a/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp b/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp index 42d676f4a00..7f698ac1cd1 100644 --- a/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp +++ b/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp @@ -19,11 +19,17 @@ TEST_F(GISelMITest, TestKnownBitsCst) { unsigned CopyReg = Copies[Copies.size() - 1]; MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); unsigned SrcReg = FinalCopy->getOperand(1).getReg(); + unsigned DstReg = FinalCopy->getOperand(1).getReg(); GISelKnownBits Info(*MF); KnownBits Res = Info.getKnownBits(SrcReg); EXPECT_EQ((uint64_t)1, Res.One.getZExtValue()); EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue()); + + KnownBits Res2 = Info.getKnownBits(DstReg); + EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); + EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); } + TEST_F(GISelMITest, TestKnownBitsPtrToIntViceVersa) { StringRef MIRString = " %3:_(s16) = G_CONSTANT i16 256\n" " %4:_(p0) = G_INTTOPTR %3\n" -- 2.50.1