From 3d7650ecd0f77d1906ecb549cc6e6e8e0e00ca06 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Mon, 6 Feb 2017 23:18:57 +0000 Subject: [PATCH] [Hexagon] Adding gp+ to the syntax of gp-relative instructions Patch by Colin LeMahieu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294258 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Hexagon/AsmParser/HexagonAsmParser.cpp | 56 +++++ lib/Target/Hexagon/HexagonInstrInfoV4.td | 18 +- test/CodeGen/Hexagon/float-amode.ll | 4 +- test/CodeGen/Hexagon/gp-rel.ll | 4 +- test/CodeGen/Hexagon/section_7275.ll | 10 +- test/CodeGen/Hexagon/static.ll | 6 +- test/MC/Disassembler/Hexagon/ld.txt | 12 +- test/MC/Disassembler/Hexagon/nv_st.txt | 6 +- test/MC/Disassembler/Hexagon/st.txt | 10 +- test/MC/Hexagon/decode_acc_type.s | 150 +++++++++++++ test/MC/Hexagon/extender.s | 210 ++++++++++++++++++ test/MC/Hexagon/instructions/ld.s | 15 +- test/MC/Hexagon/instructions/nv_st.s | 6 +- test/MC/Hexagon/instructions/st.s | 10 +- test/MC/Hexagon/load-GPRel.s | 33 +++ test/MC/Hexagon/parse-pound-hi.s | 60 +++++ test/MC/Hexagon/store-GPRel.s | 46 ++++ test/MC/Hexagon/two-extenders.s | 135 +++++++++++ 18 files changed, 743 insertions(+), 48 deletions(-) create mode 100644 test/MC/Hexagon/decode_acc_type.s create mode 100644 test/MC/Hexagon/extender.s create mode 100644 test/MC/Hexagon/load-GPRel.s create mode 100644 test/MC/Hexagon/parse-pound-hi.s create mode 100644 test/MC/Hexagon/store-GPRel.s create mode 100644 test/MC/Hexagon/two-extenders.s diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index b6201ebf038..6998383f08e 100644 --- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -2142,6 +2142,62 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, Inst = TmpInst; break; } + case Hexagon::PS_loadrubabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrubgp); + break; + case Hexagon::PS_loadrbabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrbgp); + break; + case Hexagon::PS_loadruhabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadruhgp); + break; + case Hexagon::PS_loadrhabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrhgp); + break; + case Hexagon::PS_loadriabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrigp); + break; + case Hexagon::PS_loadrdabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrdgp); + break; + case Hexagon::PS_storerbabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerbgp); + break; + case Hexagon::PS_storerhabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerhgp); + break; + case Hexagon::PS_storerfabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerfgp); + break; + case Hexagon::PS_storeriabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerigp); + break; + case Hexagon::PS_storerdabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerdgp); + break; + case Hexagon::PS_storerbnewabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerbnewgp); + break; + case Hexagon::PS_storerhnewabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerhnewgp); + break; + case Hexagon::PS_storerinewabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerinewgp); + break; } // switch return Match_Success; diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 85d57baecd8..46f2b525442 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -2532,7 +2532,7 @@ let hasSideEffects = 0, isPredicable = 1 in class T_StoreAbsGP MajOp, bit isAbs, bit isHalf> : STInst<(outs), (ins ImmOp:$addr, RC:$src), - mnemonic # "(#$addr) = $src"#!if(isHalf, ".h",""), + mnemonic # "(" # !if(isAbs,"","gp+") # "#$addr) = $src" # !if(isHalf,".h",""), [], "", V2LDST_tc_st_SLOT01> { bits<19> addr; bits<5> src; @@ -2646,9 +2646,9 @@ multiclass ST_AbsMajOp> +class T_StoreAbsGP_NV MajOp, bit isAbs> : NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src), - mnemonic #"(#$addr) = $src.new", + mnemonic #"(" # !if(isAbs, "", "gp+") # "#$addr) = $src.new", [], "", V2LDST_tc_st_SLOT0> { bits<19> addr; bits<3> src; @@ -2716,7 +2716,7 @@ class T_StoreAbs_NV_Pred MajOp, bit isNot, bit isNew> // absolute addressing. //===----------------------------------------------------------------------===// class T_StoreAbs_NV MajOp> - : T_StoreAbsGP_NV , AddrModeRel { + : T_StoreAbsGP_NV , AddrModeRel { string ImmOpStr = !cast(ImmOp); let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, @@ -2798,7 +2798,7 @@ multiclass ST_GP ; // New-value store - def NAME#newgp : T_StoreAbsGP_NV ; + def NAME#newgp : T_StoreAbsGP_NV ; } } @@ -2825,9 +2825,9 @@ def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs, //===----------------------------------------------------------------------===// let isPredicable = 1, hasSideEffects = 0 in class T_LoadAbsGP MajOp> + bits<3> MajOp, bit isAbs> : LDInst <(outs RC:$dst), (ins ImmOp:$addr), - "$dst = "#mnemonic# "(#$addr)", + "$dst = " # mnemonic # "(" # !if(isAbs, "", "gp+") # "#$addr)", [], "", V2LDST_tc_ld_SLOT01> { bits<5> dst; bits<19> addr; @@ -2860,7 +2860,7 @@ class T_LoadAbsGP MajOp> - : T_LoadAbsGP , AddrModeRel { + : T_LoadAbsGP , AddrModeRel { string ImmOpStr = !cast(ImmOp); let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, @@ -2956,7 +2956,7 @@ defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>; let isAsmParserOnly = 1, Uses = [GP] in class T_LoadGP MajOp> - : T_LoadAbsGP , PredNewRel { + : T_LoadAbsGP , PredNewRel { let BaseOpcode = BaseOp#_abs; } diff --git a/test/CodeGen/Hexagon/float-amode.ll b/test/CodeGen/Hexagon/float-amode.ll index 9804f48349f..5f13e048f9c 100644 --- a/test/CodeGen/Hexagon/float-amode.ll +++ b/test/CodeGen/Hexagon/float-amode.ll @@ -54,9 +54,9 @@ entry: } ; CHECK-LABEL: test3 -; CHECK: [[REG31:(r[0-9]+)]]{{ *}}={{ *}}memw(#b) +; CHECK: [[REG31:(r[0-9]+)]]{{ *}}={{ *}}memw(gp+#b) ; CHECK: [[REG32:(r[0-9]+)]] = sfadd({{.*}}[[REG31]] -; CHECK: memw(#a) = [[REG32]] +; CHECK: memw(gp+#a) = [[REG32]] ; Function Attrs: norecurse nounwind define void @test3(%struct.matrix_params* nocapture readonly %params, i32 %col1) { diff --git a/test/CodeGen/Hexagon/gp-rel.ll b/test/CodeGen/Hexagon/gp-rel.ll index bb7cb182bf1..00f57797b6f 100644 --- a/test/CodeGen/Hexagon/gp-rel.ll +++ b/test/CodeGen/Hexagon/gp-rel.ll @@ -7,8 +7,8 @@ define i32 @foo(i32 %p) #0 { entry: -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#a) -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#b) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(gp+#a) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(gp+#b) ; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}} %0 = load i32, i32* @a, align 4 %1 = load i32, i32* @b, align 4 diff --git a/test/CodeGen/Hexagon/section_7275.ll b/test/CodeGen/Hexagon/section_7275.ll index c2b80ae3f69..1806f1e9c84 100644 --- a/test/CodeGen/Hexagon/section_7275.ll +++ b/test/CodeGen/Hexagon/section_7275.ll @@ -8,13 +8,13 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK-LABEL: foo ; CHECK-DAG: memw(##b) -; CHECK-DAG: memw(#d) +; CHECK-DAG: memw(gp+#d) ; CHECK-DAG: memw(##g) -; CHECK-DAG: memw(#h) -; CHECK-DAG: memw(#f) +; CHECK-DAG: memw(gp+#h) +; CHECK-DAG: memw(gp+#f) ; CHECK-DAG: memw(##e) -; CHECK-DAG: memw(#a) -; CHECK-DAG: memw(#c) +; CHECK-DAG: memw(gp+#a) +; CHECK-DAG: memw(gp+#c) ; CHECK-LABEL: bar ; CHECK: memw(##b) diff --git a/test/CodeGen/Hexagon/static.ll b/test/CodeGen/Hexagon/static.ll index c3237b74888..15aab434158 100644 --- a/test/CodeGen/Hexagon/static.ll +++ b/test/CodeGen/Hexagon/static.ll @@ -4,9 +4,9 @@ @acc = external global i32 @val = external global i32 -; CHECK-DAG: memw(#num) -; CHECK-DAG: memw(#acc) -; CHECK-DAG: memw(#val) +; CHECK-DAG: memw(gp+#num) +; CHECK-DAG: memw(gp+#acc) +; CHECK-DAG: memw(gp+#val) define void @foo() nounwind { entry: diff --git a/test/MC/Disassembler/Hexagon/ld.txt b/test/MC/Disassembler/Hexagon/ld.txt index 56e00fd94f5..91bb250733f 100644 --- a/test/MC/Disassembler/Hexagon/ld.txt +++ b/test/MC/Disassembler/Hexagon/ld.txt @@ -5,7 +5,7 @@ 0x90 0xff 0xd5 0x3a # CHECK: r17:16 = memd(r21 + r31<<#3) 0xb0 0xc2 0xc0 0x49 -# CHECK: r17:16 = memd(#168) +# CHECK: r17:16 = memd(gp+#168) 0x02 0x40 0x00 0x00 0x10 0xc5 0xc0 0x49 # CHECK: r17:16 = memd(##168) 0xd0 0xc0 0xd5 0x91 @@ -59,7 +59,7 @@ 0x91 0xff 0x15 0x3a # CHECK: r17 = memb(r21 + r31<<#3) 0xb1 0xc2 0x00 0x49 -# CHECK: r17 = memb(#21) +# CHECK: r17 = memb(gp+#21) 0x00 0x40 0x00 0x00 0xb1 0xc2 0x00 0x49 # CHECK: r17 = memb(##21) 0xf1 0xc3 0x15 0x91 @@ -129,7 +129,7 @@ 0x91 0xff 0x55 0x3a # CHECK: r17 = memh(r21 + r31<<#3) 0xb1 0xc2 0x40 0x49 -# CHECK: r17 = memh(#42) +# CHECK: r17 = memh(gp+#42) 0x00 0x40 0x00 0x00 0x51 0xc5 0x40 0x49 # CHECK: r17 = memh(##42) 0xf1 0xc3 0x55 0x91 @@ -183,7 +183,7 @@ 0x91 0xff 0x35 0x3a # CHECK: r17 = memub(r21 + r31<<#3) 0xb1 0xc2 0x20 0x49 -# CHECK: r17 = memub(#21) +# CHECK: r17 = memub(gp+#21) 0x00 0x40 0x00 0x00 0xb1 0xc2 0x20 0x49 # CHECK: r17 = memub(##21) 0xf1 0xc3 0x35 0x91 @@ -237,7 +237,7 @@ 0x91 0xff 0x75 0x3a # CHECK: r17 = memuh(r21 + r31<<#3) 0xb1 0xc2 0x60 0x49 -# CHECK: r17 = memuh(#42) +# CHECK: r17 = memuh(gp+#42) 0x00 0x40 0x00 0x00 0x51 0xc5 0x60 0x49 # CHECK: r17 = memuh(##42) 0xb1 0xc2 0x75 0x91 @@ -291,7 +291,7 @@ 0x91 0xff 0x95 0x3a # CHECK: r17 = memw(r21 + r31<<#3) 0xb1 0xc2 0x80 0x49 -# CHECK: r17 = memw(#84) +# CHECK: r17 = memw(gp+#84) 0x01 0x40 0x00 0x00 0x91 0xc2 0x80 0x49 # CHECK: r17 = memw(##84) 0xb1 0xc2 0x95 0x91 diff --git a/test/MC/Disassembler/Hexagon/nv_st.txt b/test/MC/Disassembler/Hexagon/nv_st.txt index 3a767f33b36..9e3f9a776b8 100644 --- a/test/MC/Disassembler/Hexagon/nv_st.txt +++ b/test/MC/Disassembler/Hexagon/nv_st.txt @@ -7,7 +7,7 @@ # CHECK-NEXT: memb(r17 + r21<<#3) = r31.new 0x1f 0x40 0x7f 0x70 0x11 0xc2 0xa0 0x48 # CHECK: r31 = r31 -# CHECK-NEXT: memb(#17) = r31.new +# CHECK-NEXT: memb(gp+#17) = r31.new 0x1f 0x40 0x7f 0x70 0x15 0xc2 0xb1 0xa1 # CHECK: r31 = r31 # CHECK-NEXT: memb(r17+#21) = r31.new @@ -77,7 +77,7 @@ # CHECK-NEXT: memh(r17 + r21<<#3) = r31.new 0x1f 0x40 0x7f 0x70 0x15 0xca 0xa0 0x48 # CHECK: r31 = r31 -# CHECK-NEXT: memh(#42) = r31.new +# CHECK-NEXT: memh(gp+#42) = r31.new 0x1f 0x40 0x7f 0x70 0x15 0xca 0xb1 0xa1 # CHECK: r31 = r31 # CHECK-NEXT: memh(r17+#42) = r31.new @@ -147,7 +147,7 @@ # CHECK-NEXT: memw(r17 + r21<<#3) = r31.new 0x1f 0x40 0x7f 0x70 0x15 0xd2 0xa0 0x48 # CHECK: r31 = r31 -# CHECK-NEXT: memw(#84) = r31.new +# CHECK-NEXT: memw(gp+#84) = r31.new 0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1 # CHECK: r31 = r31 # CHECK-NEXT: memw(r17+#84) = r31.new diff --git a/test/MC/Disassembler/Hexagon/st.txt b/test/MC/Disassembler/Hexagon/st.txt index 6d9074a05ef..601047e88a2 100644 --- a/test/MC/Disassembler/Hexagon/st.txt +++ b/test/MC/Disassembler/Hexagon/st.txt @@ -5,7 +5,7 @@ 0x9e 0xf5 0xd1 0x3b # CHECK: memd(r17 + r21<<#3) = r31:30 0x28 0xd4 0xc0 0x48 -# CHECK: memd(#320) = r21:20 +# CHECK: memd(gp+#320) = r21:20 0x02 0x40 0x00 0x00 0x28 0xd4 0xc0 0x48 # CHECK: memd(##168) = r21:20 0x15 0xd4 0xd1 0xa1 @@ -71,7 +71,7 @@ 0x9f 0xca 0x11 0x3c # CHECK: memb(r17+#21)=#31 0x15 0xd5 0x00 0x48 -# CHECK: memb(#21) = r21 +# CHECK: memb(gp+#21) = r21 0x00 0x40 0x00 0x00 0x15 0xd5 0x00 0x48 # CHECK: memb(##21) = r21 0x15 0xd5 0x11 0xa1 @@ -153,9 +153,9 @@ 0x00 0x40 0x00 0x00 0x2a 0xd5 0x60 0x48 # CHECK: memh(##42) = r21.h 0x2a 0xd5 0x40 0x48 -# CHECK: memh(#84) = r21 +# CHECK: memh(gp+#84) = r21 0x2a 0xd5 0x60 0x48 -# CHECK: memh(#84) = r21.h +# CHECK: memh(gp+#84) = r21.h 0x15 0xdf 0x51 0xa1 # CHECK: memh(r17+#42) = r31 0x15 0xdf 0x71 0xa1 @@ -283,7 +283,7 @@ 0x9f 0xca 0x51 0x3c # CHECK: memw(r17{{ *}}+{{ *}}#84)=#31 0x15 0xdf 0x80 0x48 -# CHECK: memw(#84) = r31 +# CHECK: memw(gp+#84) = r31 0x01 0x40 0x00 0x00 0x14 0xd5 0x80 0x48 # CHECK: memw(##84) = r21 0x9f 0xca 0x51 0x3c diff --git a/test/MC/Hexagon/decode_acc_type.s b/test/MC/Hexagon/decode_acc_type.s new file mode 100644 index 00000000000..84d0abc0e18 --- /dev/null +++ b/test/MC/Hexagon/decode_acc_type.s @@ -0,0 +1,150 @@ +# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# + +# Currently ignore if there is one or two #'s + + r7 = memw(gp+#192) +# CHECK: r7 = memw(gp+#192) + + r3:2 = memd(gp+#64) +# CHECK: r3:2 = memd(gp+#64) + + { p3 = p1; r8 = #2; if (p3.new) memw(##8) = r8.new } +# CHECK: if (p3.new) memw({{..}}8) = r8 + + { p3 = p1; r8 = #2; if (!p3.new) memw(##8) = r8.new } +# CHECK: if (!p3.new) memw({{..}}8) = r8.new + + { r8 = #2; if (p3) memw(##8) = r8.new } +# CHECK: if (p3) memw({{..}}8) = r8.new + + { r8 = #2; if (!p3) memw(##8) = r8.new } +# CHECK: if (!p3) memw({{..}}8) = r8.new + + { p3 = p1; r8 = #2; if (p3.new) memh(##8) = r8.new } +# CHECK: if (p3.new) memh({{..}}8) = r8.new + + { p3 = p1; r8 = #2; if (!p3.new) memh(##8) = r8.new } +# CHECK: if (!p3.new) memh({{..}}8) = r8.new + + { r8 = #2; if (p3) memh(##8) = r8.new } +# CHECK: memh({{..}}8) = r8.new + + { r8 = #2; if (!p3) memh(##8) = r8.new } +# CHECK: if (!p3) memh({{..}}8) = r8.new + + { p3 = p1; r8 = #2; if (p3.new) memb(##8) = r8.new } +# CHECK: if (p3.new) memb({{..}}8) = r8.new + + { p3 = p1; r8 = #2; if (!p3.new) memb(##8) = r8.new } +# CHECK: if (!p3.new) memb({{..}}8) = r8.new + + { r8 = #2; if (p3) memb(##8) = r8.new } +# CHECK: if (p3) memb({{..}}8) = r8.new + + { r8 = #2; if (!p3) memb(##8) = r8.new } +# CHECK: if (!p3) memb({{..}}8) = r8.new + + { if (p3) memw(##8) = r8 } +# CHECK: if (p3) memw({{..}}8) = r8 + + { if (!p3) memw(##8) = r8 } +# CHECK: if (!p3) memw({{..}}8) = r8 + + { p3 = p1; if (p3.new) memw(##8) = r8 } +# CHECK: if (p3.new) memw({{..}}8) = r8 + + { p3 = p1; if (!p3.new) memw(##8) = r8 } +# CHECK: if (!p3.new) memw({{..}}8) = r8 + + + if (!p2) r14 = memb(##48) +# CHECK: if (!p2) r14 = memb({{..}}48) + + if (p2) r14 = memb(##48) +# CHECK: if (p2) r14 = memb({{..}}48) + + {p2 = p0; if (!p2.new) r14 = memb(##48) } +# CHECK: if (!p2.new) r14 = memb({{..}}48) + + {p3 = p2; if (p3.new) r14 = memb(##48) } +# CHECK: if (p3.new) r14 = memb({{..}}48) + + + if (!p2) r14 = memh(##48) +# CHECK: if (!p2) r14 = memh({{..}}48) + + if (p2) r14 = memh(##48) +# CHECK: if (p2) r14 = memh({{..}}48) + + {p2 = p0; if (!p2.new) r14 = memh(##48) } +# CHECK: if (!p2.new) r14 = memh({{..}}48) + + {p3 = p2; if (p3.new) r14 = memh(##48) } +# CHECK: if (p3.new) r14 = memh({{..}}48) + + + if (!p2) r14 = memub(##48) +# CHECK: if (!p2) r14 = memub({{..}}48) + + if (p2) r14 = memub(##48) +# CHECK: if (p2) r14 = memub({{..}}48) + + {p2 = p0; if (!p2.new) r14 = memub(##48) } +# CHECK: if (!p2.new) r14 = memub({{..}}48) + + {p3 = p2; if (p3.new) r14 = memub(##48) } +# CHECK: if (p3.new) r14 = memub({{..}}48) + + + if (!p2) r14 = memuh(##48) +# CHECK: if (!p2) r14 = memuh({{..}}48) + + if (p2) r14 = memuh(##48) +# CHECK: if (p2) r14 = memuh({{..}}48) + + {p2 = p0; if (!p2.new) r14 = memuh(##48) } +# CHECK: if (!p2.new) r14 = memuh({{..}}48) + + {p3 = p2; if (p3.new) r14 = memuh(##48) } +# CHECK: r14 = memuh({{..}}48) + + + if (!p2) r14 = memw(##48) +# CHECK: if (!p2) r14 = memw({{..}}48) + + if (p2) r14 = memw(##48) +# CHECK: if (p2) r14 = memw({{..}}48) + + {p2 = p0; if (!p2.new) r14 = memw(##48) } +# CHECK: if (!p2.new) r14 = memw({{..}}48) + + {p3 = p2; if (p3.new) r14 = memw(##48) } +# CHECK: if (p3.new) r14 = memw({{..}}48) + + r7 = memh(##32) +# CHECK: r7 = memh(##32) + r7 = memuh(##32) +# CHECK: r7 = memuh(##32) + + memd(##32) = r15:14 +# CHECK: memd(##32) = r15:14 + + {r2 = #9; memw(##32) = r2.new} +# CHECK: memw(##32) = r2.new + + {r2 = #9; memb(##32) = r2.new} +# CHECK: memb(##32) = r2.new + + memw(##32) = r15 +# CHECK: memw(##32) = r15 + + memh(##32) = r16 +# CHECK: memh(##32) = r16 + + memb(##32) = r17 +# CHECK: memb(##32) = r17 + + + r3:2 = interleave(r31:30) +# CHECK: r3:2 = interleave(r31:30) diff --git a/test/MC/Hexagon/extender.s b/test/MC/Hexagon/extender.s new file mode 100644 index 00000000000..f807dbe0cdd --- /dev/null +++ b/test/MC/Hexagon/extender.s @@ -0,0 +1,210 @@ +# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# + +# STrib_abs_V4 +{ + memb(##1024056) = r0 +} + +# CHECK: immext(#1024000) +# CHECK: memb(##1024056) = r0 + +# S2_storerbgp +{ + memb(GP + #56) = r0 +} + +# CHECK: memb(gp+#56) = r0 + +# STrih_abs_V4 +{ + memh(##1024056) = r0 +} + +# CHECK: immext(#1024000) +# CHECK: memh(##1024056) = r0 + +# S2_storerhgp +{ + memh(GP + #56) = r0 +} + +# CHECK: memh(gp+#56) = r0 + +# STriw_abs_V4 +{ + memw(##1024056) = r0 +} + +# CHECK: immext(#1024000) +# CHECK: memw(##1024056) = r0 + +# S2_storerigp +{ + memw(GP + #56) = r0 +} + +# CHECK: memw(gp+#56) = r0 + +# STrib_abs_nv_V4 +{ + r0 = #1 + memb(##1024056) = r0.new +} + +# CHECK: r0 = #1 +# CHECK: immext(#1024000) +# CHECK: memb(##1024056) = r0.new + +# S2_storerbnewgp +{ + r0 = #1 + memb(GP + #56) = r0.new +} + +# CHECK: r0 = #1 +# CHECK: memb(gp+#56) = r0.new + +# STrih_abs_nv_V4 +{ + r0 = #1 + memh(##1024056) = r0.new +} + +# CHECK: r0 = #1 +# CHECK: immext(#1024000) +# CHECK: memh(##1024056) = r0.new + +# S2_storerhnewgp +{ + r0 = #1 + memh(GP + #56) = r0.new +} + +# CHECK: r0 = #1 +# CHECK: memh(gp+#56) = r0.new + +# STriw_abs_nv_V4 +{ + r0 = #1 + memw(##1024056) = r0.new +} + +# CHECK: r0 = #1 +# CHECK: immext(#1024000) +# CHECK: memw(##1024056) = r0.new + +# S2_storerinewgp +{ + r0 = #1 + memw(GP + #56) = r0.new +} + +# CHECK: r0 = #1 +# CHECK: memw(gp+#56) = r0.new + +# STrid_abs_V4 +{ + memd(##1024056) = r1:0 +} + +# CHECK: immext(#1024000) +# CHECK: memd(##1024056) = r1:0 + +# S2_storerdgp +{ + memd(GP + #56) = r1:0 +} + +# CHECK: memd(gp+#56) = r1:0 + +# LDrib_abs_V4 +{ + r0 = memb(##1024056) +} + +# CHECK: immext(#1024000) +# CHECK: r0 = memb(##1024056) + +# LDb_GP_V4 +{ + r0 = memb(GP + #56) +} + +# CHECK: r0 = memb(gp+#56) + +# LDriub_abs_V4 +{ + r0 = memub(##1024056) +} + +# CHECK: immext(#1024000) +# CHECK: r0 = memub(##1024056) + +# LDub_GP_V4 +{ + r0 = memub(GP + #56) +} + +# CHECK: r0 = memub(gp+#56) + +# LDrih_abs_V4 +{ + r0 = memh(##1024056) +} + +# CHECK: immext(#1024000) +# CHECK: r0 = memh(##1024056) + +# LDh_GP_V4 +{ + r0 = memh(GP + #56) +} + +# CHECK: r0 = memh(gp+#56) + +# LDriuh_abs_V4 +{ + r0 = memuh(##1024056) +} + +# CHECK: immext(#1024000) +# CHECK: r0 = memuh(##1024056) + +# LDuh_GP_V4 +{ + r0 = memuh(GP + #56) +} + +# CHECK: r0 = memuh(gp+#56) + +# LDriw_abs_V4 +{ + r0 = memw(##1024056) +} + +# CHECK: immext(#1024000) +# CHECK: r0 = memw(##1024056) + +# LDw_GP_V4 +{ + r0 = memw(GP + #56) +} + +# CHECK: r0 = memw(gp+#56) + +# LDrid_abs_V4 +{ + r1:0 = memd(##1024056) +} + +# CHECK: immext(#1024000) +# CHECK: r1:0 = memd(##1024056) + +# LDd_GP_V4 +{ + r1:0 = memd(GP + #56) +} + +# CHECK: r1:0 = memd(gp+#56) + diff --git a/test/MC/Hexagon/instructions/ld.s b/test/MC/Hexagon/instructions/ld.s index 2695999aa85..5d18e6a3049 100644 --- a/test/MC/Hexagon/instructions/ld.s +++ b/test/MC/Hexagon/instructions/ld.s @@ -1,6 +1,11 @@ # RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s # Hexagon Programmer's Reference Manual 11.5 LD +# Load doubleword +# CHECK: 90 ff d5 3a +r17:16 = memd(r21 + r31<<#3) +# CHECK: b0 c2 c0 49 +r17:16 = memd(gp+#168) # CHECK: 02 40 00 00 # CHECK-NEXT: 10 c5 c0 49 r17:16 = memd(##168) @@ -62,7 +67,7 @@ if (!p3) r17:16 = memd(r21++#40) # CHECK: 91 ff 15 3a r17 = memb(r21 + r31<<#3) # CHECK: b1 c2 00 49 -r17 = memb(#21) +r17 = memb(gp+#21) # CHECK: 00 40 00 00 # CHECK-NEXT: b1 c2 00 49 r17 = memb(##21) @@ -140,7 +145,7 @@ r17:16 = memh_fifo(r21 ++ I:circ(m1)) # CHECK: 91 ff 55 3a r17 = memh(r21 + r31<<#3) # CHECK: b1 c2 40 49 -r17 = memh(#42) +r17 = memh(gp+#42) # CHECK: 00 40 00 00 # CHECK-NEXT: 51 c5 40 49 r17 = memh(##42) @@ -202,7 +207,7 @@ if (!p3) r17 = memh(r21 + #62) # CHECK: 91 ff 35 3a r17 = memub(r21 + r31<<#3) # CHECK: b1 c2 20 49 -r17 = memub(#21) +r17 = memub(gp+#21) # CHECK: 00 40 00 00 # CHECK-NEXT: b1 c2 20 49 r17 = memub(##21) @@ -264,7 +269,7 @@ if (!p3) r17 = memub(r21++#5) # CHECK: 91 ff 75 3a r17 = memuh(r21 + r31<<#3) # CHECK: b1 c2 60 49 -r17 = memuh(#42) +r17 = memuh(gp+#42) # CHECK: 00 40 00 00 # CHECK-NEXT: 51 c5 60 49 r17 = memuh(##42) @@ -326,7 +331,7 @@ if (!p3) r17 = memuh(r21++#10) # CHECK: 91 ff 95 3a r17 = memw(r21 + r31<<#3) # CHECK: b1 c2 80 49 -r17 = memw(#84) +r17 = memw(gp+#84) # CHECK: 01 40 00 00 # CHECK-NEXT: 91 c2 80 49 r17 = memw(##84) diff --git a/test/MC/Hexagon/instructions/nv_st.s b/test/MC/Hexagon/instructions/nv_st.s index 4ff490024a8..46ab31ef2f7 100644 --- a/test/MC/Hexagon/instructions/nv_st.s +++ b/test/MC/Hexagon/instructions/nv_st.s @@ -9,7 +9,7 @@ # CHECK: 1f 40 7f 70 # CHECK-NEXT: 11 c2 a0 48 { r31 = r31 - memb(#17) = r31.new } + memb(gp+#17) = r31.new } # CHECK: 1f 40 7f 70 # CHECK-NEXT: 15 c2 b1 a1 { r31 = r31 @@ -105,7 +105,7 @@ # CHECK: 1f 40 7f 70 # CHECK-NEXT: 15 ca a0 48 { r31 = r31 - memh(#42) = r31.new } + memh(gp+#42) = r31.new } # CHECK: 1f 40 7f 70 # CHECK-NEXT: 15 ca b1 a1 { r31 = r31 @@ -201,7 +201,7 @@ # CHECK: 1f 40 7f 70 # CHECK-NEXT: 15 d2 a0 48 { r31 = r31 - memw(#84) = r31.new } + memw(gp+#84) = r31.new } # CHECK: 1f 40 7f 70 # CHECK-NEXT: 15 d2 b1 a1 { r31 = r31 diff --git a/test/MC/Hexagon/instructions/st.s b/test/MC/Hexagon/instructions/st.s index 3b5e8ee1810..6ea6e9f47f7 100644 --- a/test/MC/Hexagon/instructions/st.s +++ b/test/MC/Hexagon/instructions/st.s @@ -5,7 +5,7 @@ # CHECK: 9e f5 d1 3b memd(r17 + r21<<#3) = r31:30 # CHECK: 28 d4 c0 48 -memd(#320) = r21:20 +memd(gp+#320) = r21:20 # CHECK: 02 40 00 00 # CHECK-NEXT: 28 d4 c0 48 memd(##168) = r21:20 @@ -83,7 +83,7 @@ memb(r17 + r21<<#3) = r31 # CHECK: 9f ca 11 3c memb(r17+#21)=#31 # CHECK: 15 d5 00 48 -memb(#21) = r21 +memb(gp+#21) = r21 # CHECK: 00 40 00 00 # CHECK-NEXT: 15 d5 00 48 memb(##21) = r21 @@ -183,9 +183,9 @@ memh(##42) = r21 # CHECK-NEXT: 2a d5 60 48 memh(##42) = r21.h # CHECK: 2a d5 40 48 -memh(#84) = r21 +memh(gp+#84) = r21 # CHECK: 2a d5 60 48 -memh(#84) = r21.h +memh(gp+#84) = r21.h # CHECK: 15 df 51 a1 memh(r17+#42) = r31 # CHECK: 15 df 71 a1 @@ -341,7 +341,7 @@ memw(r17 + r21<<#3) = r31 # CHECK: 9f ca 51 3c memw(r17+#84)=#31 # CHECK: 15 df 80 48 -memw(#84) = r31 +memw(gp+#84) = r31 # CHECK: 01 40 00 00 # CHECK-NEXT: 14 d5 80 48 memw(##84) = r21 diff --git a/test/MC/Hexagon/load-GPRel.s b/test/MC/Hexagon/load-GPRel.s new file mode 100644 index 00000000000..88f33cd6d7e --- /dev/null +++ b/test/MC/Hexagon/load-GPRel.s @@ -0,0 +1,33 @@ +#RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s + +# Check encoding bits for GP-relative loads. + +#CHECK: 4fc6ff8c { r13:12 = memd(gp+#421856) } +r13:12 = memd(gp+#421856) +#CHECK: 4fc6ff8c { r13:12 = memd(gp+#421856) } +r13:12 = memd(#421856) + +#CHECK: 4d1ac4d2 { r18 = memb(gp+#46118) } +r18 = memb(gp+#46118) +#CHECK: 4d1ac4d2 { r18 = memb(gp+#46118) } +r18 = memb(#46118) + +#CHECK: 4d81f772 { r18 = memw(gp+#134892) } +r18 = memw(gp+#134892) +#CHECK: 4d81f772 { r18 = memw(gp+#134892) } +r18 = memw(#134892) + +#CHECK: 497de287 { r7 = memuh(gp+#30248) } +r7 = memuh(gp+#30248) +#CHECK: 497de287 { r7 = memuh(gp+#30248) } +r7 = memuh(#30248) + +#CHECK: 4b43e87a { r26 = memh(gp+#36486) } +r26 = memh(gp+#36486) +#CHECK: 4b43e87a { r26 = memh(gp+#36486) } +r26 = memh(#36486) + +#CHECK: 4f37d07f { r31 = memub(gp+#61059) } +r31 = memub(gp+#61059) +#CHECK: 4f37d07f { r31 = memub(gp+#61059) } +r31 = memub(#61059) diff --git a/test/MC/Hexagon/parse-pound-hi.s b/test/MC/Hexagon/parse-pound-hi.s new file mode 100644 index 00000000000..5c6786481c7 --- /dev/null +++ b/test/MC/Hexagon/parse-pound-hi.s @@ -0,0 +1,60 @@ +# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s + + memw(gp+#hi_htc_version) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + memw(gp+#HI) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + r3 = memw(gp+#HI) +#CHECK: 4980c003 { r3 = memw(gp+#0) } + memw(gp+#HI_x) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + r3 = memw(gp+#HI_x) +#CHECK: 4980c003 { r3 = memw(gp+#0) } + memw(gp+#hi) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + r3 = memw(gp+#hi) +#CHECK: 4980c003 { r3 = memw(gp+#0) } + memw(gp+#hi_x) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + r3 = memw(gp+#hi_x) +#CHECK: 4980c003 { r3 = memw(gp+#0) } + memw(gp+#lo) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + r3 = memw(gp+#lo) +#CHECK: 4980c003 { r3 = memw(gp+#0) } + memw(gp+#lo_x) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + r3 = memw(gp+#lo_x) +#CHECK: 4980c003 { r3 = memw(gp+#0) } + memw(gp+#LO) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + r3 = memw(gp+#lo) +#CHECK: 4980c003 { r3 = memw(gp+#0) } + memw(gp+#LO_x) = r3 +#CHECK: 4880c300 { memw(gp+#0) = r3 } + r3 = memw(gp+#LO_x) +#CHECK: 4980c003 { r3 = memw(gp+#0) } + r16.h = #HI(0x405000) +#CHECK: 7230c040 { r16.h = #64 } + r16.h = #HI (0x405000) +#CHECK: 7230c040 { r16.h = #64 } + r16.h = #hi(0x405000) +#CHECK: 7230c040 { r16.h = #64 } + r16.h = #hi (0x405000) +#CHECK: 7230c040 { r16.h = #64 } + r16.l = #LO(0x405020) +#CHECK: 7170d020 { r16.l = #20512 } + r16.l = #LO (0x405020) +#CHECK: 7170d020 { r16.l = #20512 } + r16.l = #lo(0x405020) +#CHECK: 7170d020 { r16.l = #20512 } + r16.l = #lo (0x405020) +#CHECK: 7170d020 { r16.l = #20512 } + +{ + r19.h = #HI(-559030611) + memw(r17+#0) = r19.new +} +# CHECK: 72f35ead { r19.h = #57005 +# CHECK: a1b1d200 memw(r17+#0) = r19.new } + diff --git a/test/MC/Hexagon/store-GPRel.s b/test/MC/Hexagon/store-GPRel.s new file mode 100644 index 00000000000..090a6d0059b --- /dev/null +++ b/test/MC/Hexagon/store-GPRel.s @@ -0,0 +1,46 @@ +#RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s + +# Check encoding bits for gp-rel stores. + +#CHECK: 4ab3f229 memw(gp+#105636) = r12.new +{ r12 = add(r0,r19) + memw(gp+#105636) = r12.new } + +#CHECK: 4ab3f229 memw(gp+#105636) = r12.new +{ r12 = add(r0,r19) + memw(#105636) = r12.new } + +#CHECK: 4ebdca35 memh(gp+#128106) = r6.new +{ r6 = add(r18,r13) + memh(gp+#128106) = r6.new } + +#CHECK: 4ebdca35 memh(gp+#128106) = r6.new +{ r6 = add(r18,r13) + memh(#128106) = r6.new } + +#CHECK: 4eb3e2fc memb(gp+#59388) = r17.new +{ r17 = add(r26,r18) + memb(gp+#59388) = r17.new } +#CHECK: 4eb3e2fc memb(gp+#59388) = r17.new +{ r17 = add(r26,r18) + memb(#59388) = r17.new } + +#CHECK: 4ad2ea01 { memd(gp+#206856) = r11:10 +{ memd(gp+#206856) = r11:10 } +#CHECK: 4ad2ea01 { memd(gp+#206856) = r11:10 +{ memd(#206856) = r11:10 } + +#CHECK: 4c9dfa1e { memw(gp+#191608) = r26 +{ memw(gp+#191608) = r26 } +#CHECK: 4c9dfa1e { memw(gp+#191608) = r26 +{ memw(#191608) = r26 } + +#CHECK: 4855cfdc { memh(gp+#21944) = r15 +{ memh(gp+#21944) = r15 } +#CHECK: 4855cfdc { memh(gp+#21944) = r15 +{ memh(#21944) = r15 } + +#CHECK: 4a00cea2 { memb(gp+#16546) = r14 +{ memb(gp+#16546) = r14 } +#CHECK: 4a00cea2 { memb(gp+#16546) = r14 +{ memb(#16546) = r14 } diff --git a/test/MC/Hexagon/two-extenders.s b/test/MC/Hexagon/two-extenders.s new file mode 100644 index 00000000000..49016639de1 --- /dev/null +++ b/test/MC/Hexagon/two-extenders.s @@ -0,0 +1,135 @@ +# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# + +# In packets with two extensions assembler is not extending both instructions +# + +//['D_DUMMY,C4_or_or,L4_ploadrbtnew_abs,S2_storerfgp'] +{ + if (p3) r23 = memb(##2164335510) + memh(##1696682668) = r28.h +} +# CHECK: { immext(#2164335488) +# CHECK: if (p3) r23 = memb(##2164335510) +# CHECK: immext(#1696682624) +# CHECK: memh(##1696682668) = r28.h } + +//['D_DUMMY,C4_or_or,L4_ploadrbtnew_abs,S2_storerfgp'] +{ + if (p3.new) r23 = memb(##2164335510) + p3 = or(p2,or(p3, p0)) +} +# CHECK: { p3 = or(p2, or(p3, p0)) +# CHECK: immext(#2164335488) +# CHECK: if (p3.new) r23 = memb(##2164335510) } + + +# -------------------------- Non-extended cases: +# -------------------------- Use GP and non GP notation + +R2 = memb(gp+#0x1000) +# CHECK: { r2 = memb(gp+#4096) } + +R3 = memh(gp+#0x1000) +# CHECK: { r3 = memh(gp+#4096) } + +r4 = memub(gp+#0x1000) +# CHECK: { r4 = memub(gp+#4096) } + +r5 = memuh(gp+#0x1000) +# CHECK: { r5 = memuh(gp+#4096) } + +r6 = memw(gp+#0x1000) +# CHECK: { r6 = memw(gp+#4096) } + +R1:0 = memd(gp+#0x1000) +# CHECK: { r1:0 = memd(gp+#4096) } + +{R25 = #1; memb(gp+#0x1000) = R25.new} +# CHECK: { r25 = #1 +# CHECK-NEXT: memb(gp+#4096) = r25.new } + +{R26 = #1; memh(gp+#0x1000) = R26.new} +# CHECK: { r26 = #1 +# CHECK-NEXT: memh(gp+#4096) = r26.new } + +{R27 = #1; memw(gp+#0x1000) = R27.new} +# CHECK: { r27 = #1 +# CHECK-NEXT: memw(gp+#4096) = r27.new } + +memd(gp+#0x1000) = R1:0 +# CHECK: { memd(gp+#4096) = r1:0 } + +memb(gp+#0x1000) = R2 +# CHECK: { memb(gp+#4096) = r2 } + +memh(gp+#0x1000) = r3.h +# CHECK: { memh(gp+#4096) = r3.h } + +memh(gp+#0x1000) = R4 +# CHECK: { memh(gp+#4096) = r4 } + +memw(gp+#0x1000) = R5 +# CHECK: { memw(gp+#4096) = r5 } + +# -------------------------- Extended cases: +# -------------------------- Use GP and non GP notation + +R11:10 = memd(##0x1000) +# CHECK: { immext(#4096) +# CHECK-NEXT: r11:10 = memd(##4096) } + +R11 = memb(##0x1000) +# CHECK: { immext(#4096) +# CHECK-NEXT: r11 = memb(##4096) } + +R12 = memh(##0x1000) +# CHECK: { immext(#4096) +# CHECK-NEXT: r12 = memh(##4096) } + +r13 = memub(##0x1000) +# CHECK: { immext(#4096) +# CHECK-NEXT: r13 = memub(##4096) } + +r14 = memuh(##0x1000) +# CHECK: { immext(#4096) +# CHECK-NEXT: r14 = memuh(##4096) } + +r15 = memw(##0x1000) +# CHECK: { immext(#4096) +# CHECK-NEXT: r15 = memw(##4096) } + +{R22 = #1; memb(##0x1000) = R22.new} +# CHECK: { r22 = #1 +# CHECK-NEXT: immext(#4096) +# CHECK-NEXT: memb(##4096) = r22.new } + +{R23 = #1; memh(##0x1000) = R23.new} +# CHECK: { r23 = #1 +# CHECK-NEXT: immext(#4096) +# CHECK-NEXT: memh(##4096) = r23.new } + +{R24 = #1; memw(##0x1000) = R24.new} +# CHECK: { r24 = #1 +# CHECK-NEXT: immext(#4096) +# CHECK-NEXT: memw(##4096) = r24.new } + +memd(##0x1000) = R17:16 +# CHECK: { immext(#4096) +# CHECK-NEXT: memd(##4096) = r17:16 } + +memb(##0x1000) = R18 +# CHECK: { immext(#4096) +# CHECK-NEXT: memb(##4096) = r18 } + +memh(##0x1000) = r19.h +# CHECK: { immext(#4096) +# CHECK-NEXT: memh(##4096) = r19.h } + +memh(##0x1000) = R20 +# CHECK: { immext(#4096) +# CHECK-NEXT: memh(##4096) = r20 } + +memw(##0x1000) = R21 +# CHECK: { immext(#4096) +# CHECK-NEXT: memw(##4096) = r21 } -- 2.40.0