From 3a98a247384aa58487d614a2cfb323ee2a7a3e41 Mon Sep 17 00:00:00 2001 From: Geoff Norton Date: Tue, 29 Jun 2010 19:53:51 +0000 Subject: [PATCH] 2010-06-29 Geoff Norton * include/private/gc_locks.h: Implement armv6+ variants of GC_test_and_set svn path=/trunk/mono/; revision=159690 --- ChangeLog | 5 +++++ include/private/gc_locks.h | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/ChangeLog b/ChangeLog index da66ce56..4a0551b0 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2010-06-29 Geoff Norton + + * include/private/gc_locks.h: Implement armv6+ variants of + GC_test_and_set + 2010-06-14 Geoff Norton * dyn_load.c: Fix one other place where l_addr could be null on diff --git a/include/private/gc_locks.h b/include/private/gc_locks.h index 7b8e6e1b..df8736d3 100644 --- a/include/private/gc_locks.h +++ b/include/private/gc_locks.h @@ -224,6 +224,19 @@ # endif /* ALPHA */ # ifdef ARM32 inline static int GC_test_and_set(volatile unsigned int *addr) { +#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__) + int ret, tmp; + __asm__ __volatile__ ( + "1:\n" + "ldrex %0, [%3]\n" + "strex %1, %2, [%3]\n" + "teq %1, #0\n" + "bne 1b\n" + : "=&r" (ret), "=&r" (tmp) + : "r" (1), "r" (addr) + : "memory", "cc"); + return ret; +#else int oldval; /* SWP on ARM is very similar to XCHG on x86. Doesn't lock the * bus because there are no SMP ARM machines. If/when there are, @@ -234,6 +247,7 @@ : "r"(1), "r"(addr) : "memory"); return oldval; +#endif } # define GC_TEST_AND_SET_DEFINED # endif /* ARM32 */ -- 2.40.0