From 39e586b37547530add8d77fede06a1ac160e19e7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Mon, 23 Sep 2019 05:35:20 +0000
Subject: [PATCH] [X86] Remove SETEQ/SETNE canonicalization code from
 LowerIntVSETCC_AVX512 to prevent an infinite loop.

The attached test case would previous infinite loop after
r365711.

I'm going to move this to X86ISelDAGToDAG.cpp to get the setcc
to match VPTEST in 32-bit mode in a follow up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372543 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelDAGToDAG.cpp         |  4 ++--
 lib/Target/X86/X86ISelLowering.cpp         |  7 ------
 test/CodeGen/X86/avx512f-vec-test-testn.ll | 27 ++++++++++++++++++++++
 3 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 18a07eb69d0..1cff706b071 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -4098,8 +4098,8 @@ bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc,
   if (CC != ISD::SETEQ && CC != ISD::SETNE)
     return false;
 
-  // See if we're comparing against zero. This should have been canonicalized
-  // to RHS during lowering.
+  // See if we're comparing against zero.
+  // FIXME: Handle all zeros on LHS.
   if (!ISD::isBuildVectorAllZeros(Setcc.getOperand(1).getNode()))
     return false;
 
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 7dbd0c1e45d..59670d0ec3c 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -20487,13 +20487,6 @@ static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
 
   ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
 
-  // If this is a seteq make sure any build vectors of all zeros are on the RHS.
-  // This helps with vptestm matching.
-  // TODO: Should we just canonicalize the setcc during DAG combine?
-  if ((SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE) &&
-      ISD::isBuildVectorAllZeros(Op0.getNode()))
-    std::swap(Op0, Op1);
-
   // Prefer SETGT over SETLT.
   if (SetCCOpcode == ISD::SETLT) {
     SetCCOpcode = ISD::getSetCCSwappedOperands(SetCCOpcode);
diff --git a/test/CodeGen/X86/avx512f-vec-test-testn.ll b/test/CodeGen/X86/avx512f-vec-test-testn.ll
index 99edd835c89..58278dfbd41 100644
--- a/test/CodeGen/X86/avx512f-vec-test-testn.ll
+++ b/test/CodeGen/X86/avx512f-vec-test-testn.ll
@@ -214,3 +214,30 @@ entry:
   ret i16 %4
 }
 
+define <2 x i64> @setcc_commute(<2 x i64> %a) {
+; X64-LABEL: setcc_commute:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
+; X64-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; X64-NEXT:    vpsubq %xmm0, %xmm1, %xmm1
+; X64-NEXT:    vptestnmq %zmm0, %zmm0, %k1
+; X64-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; X64-NEXT:    vmovdqa %xmm1, %xmm0
+; X64-NEXT:    vzeroupper
+; X64-NEXT:    retq
+;
+; X86-LABEL: setcc_commute:
+; X86:       # %bb.0:
+; X86-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
+; X86-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; X86-NEXT:    vpsubq %xmm0, %xmm2, %xmm1
+; X86-NEXT:    vpcmpeqq %zmm0, %zmm2, %k1
+; X86-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; X86-NEXT:    vmovdqa %xmm1, %xmm0
+; X86-NEXT:    vzeroupper
+; X86-NEXT:    retl
+  %1 = sub <2 x i64> zeroinitializer, %a
+  %2 = icmp eq <2 x i64> %a, zeroinitializer
+  %3 = select <2 x i1> %2, <2 x i64> %a, <2 x i64> %1
+  ret <2 x i64> %3
+}
-- 
2.40.0