From 36e90d38604e892b461d9a9b0311b2719c922399 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 26 Jul 2019 09:41:08 +0000 Subject: [PATCH] [TargetLowering] SimplifyMultipleUseDemandedBits - add SIGN_EXTEND_INREG support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367096 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 7 +++++++ test/CodeGen/AArch64/srem-seteq.ll | 10 +++++----- test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll | 15 +++++++-------- 3 files changed, 19 insertions(+), 13 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 6020877780f..f5e8c4e0ebf 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -666,6 +666,13 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits( return Op.getOperand(1); break; } + case ISD::SIGN_EXTEND_INREG: { + // If none of the extended bits are demanded, eliminate the sextinreg. + EVT ExVT = cast(Op.getOperand(1))->getVT(); + if (DemandedBits.getActiveBits() <= ExVT.getScalarSizeInBits()) + return Op.getOperand(0); + break; + } case ISD::VECTOR_SHUFFLE: { ArrayRef ShuffleMask = cast(Op)->getMask(); diff --git a/test/CodeGen/AArch64/srem-seteq.ll b/test/CodeGen/AArch64/srem-seteq.ll index f9acec99c83..45894da89fb 100644 --- a/test/CodeGen/AArch64/srem-seteq.ll +++ b/test/CodeGen/AArch64/srem-seteq.ll @@ -101,11 +101,11 @@ define i16 @test_srem_even(i16 %X) nounwind { ; CHECK-NEXT: movk w9, #37449, lsl #16 ; CHECK-NEXT: smull x9, w8, w9 ; CHECK-NEXT: lsr x9, x9, #32 -; CHECK-NEXT: add w9, w9, w8 -; CHECK-NEXT: asr w10, w9, #3 -; CHECK-NEXT: add w9, w10, w9, lsr #31 -; CHECK-NEXT: mov w10, #14 -; CHECK-NEXT: msub w8, w9, w10, w8 +; CHECK-NEXT: add w8, w9, w8 +; CHECK-NEXT: asr w9, w8, #3 +; CHECK-NEXT: add w8, w9, w8, lsr #31 +; CHECK-NEXT: mov w9, #14 +; CHECK-NEXT: msub w8, w8, w9, w0 ; CHECK-NEXT: tst w8, #0xffff ; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret diff --git a/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll b/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll index 50d14655e71..66170aa40c0 100644 --- a/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll +++ b/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll @@ -418,8 +418,8 @@ for.body: define i32 @multi_uses(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { ; CHECK-LE-LABEL: multi_uses: ; CHECK-LE: @ %bb.0: @ %entry -; CHECK-LE-NEXT: .save {r4, r5, r7, lr} -; CHECK-LE-NEXT: push {r4, r5, r7, lr} +; CHECK-LE-NEXT: .save {r4, lr} +; CHECK-LE-NEXT: push {r4, lr} ; CHECK-LE-NEXT: cmp r0, #1 ; CHECK-LE-NEXT: blt .LBB4_4 ; CHECK-LE-NEXT: @ %bb.1: @ %for.body.preheader @@ -432,21 +432,20 @@ define i32 @multi_uses(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture r ; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-LE-NEXT: ldr r1, [r3, #2]! ; CHECK-LE-NEXT: ldr r4, [r2, #2]! -; CHECK-LE-NEXT: sxth r5, r1 -; CHECK-LE-NEXT: smlad lr, r4, r1, lr -; CHECK-LE-NEXT: eor.w r1, r5, r12 -; CHECK-LE-NEXT: muls r1, r5, r1 ; CHECK-LE-NEXT: subs r0, #1 +; CHECK-LE-NEXT: smlad lr, r4, r1, lr +; CHECK-LE-NEXT: eor.w r4, r1, r12 +; CHECK-LE-NEXT: mul r1, r4, r1 ; CHECK-LE-NEXT: lsl.w r12, r1, #16 ; CHECK-LE-NEXT: bne .LBB4_2 ; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-LE-NEXT: add.w r0, lr, r12 -; CHECK-LE-NEXT: pop {r4, r5, r7, pc} +; CHECK-LE-NEXT: pop {r4, pc} ; CHECK-LE-NEXT: .LBB4_4: ; CHECK-LE-NEXT: mov.w lr, #0 ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: add.w r0, lr, r12 -; CHECK-LE-NEXT: pop {r4, r5, r7, pc} +; CHECK-LE-NEXT: pop {r4, pc} ; ; CHECK-BE-LABEL: multi_uses: ; CHECK-BE: @ %bb.0: @ %entry -- 2.40.0