From 3375d243c2b2ed9e0df253c97dd905918e06b9d3 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 2 Oct 2017 00:44:50 +0000 Subject: [PATCH] [X86] Use _NOREX MOVZX instructions for some patterns even in 32-bit mode. This unifies the patterns between both modes. This should be effectively NFC since all the available registers in 32-bit mode statisfy this constraint. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314643 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrCompiler.td | 38 +++++------------------------- 1 file changed, 6 insertions(+), 32 deletions(-) diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index ec560a6e3ce..6f7a8d3817c 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -1488,21 +1488,16 @@ def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), Requires<[Not64BitMode]>; def : Pat<(srl GR16:$src, (i8 8)), (EXTRACT_SUBREG - (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), - sub_16bit)>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), + sub_16bit)>; def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), - (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), - (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), - (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), - (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; // h-register tricks. // For now, be conservative on x86-64 and use an h-register extract only if the @@ -1518,27 +1513,6 @@ def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), sub_32bit)>; -def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), - (MOVZX32_NOREXrr8 - (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, - Requires<[In64BitMode]>; -def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), - (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, - Requires<[In64BitMode]>; -def : Pat<(srl GR16:$src, (i8 8)), - (EXTRACT_SUBREG - (MOVZX32_NOREXrr8 - (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), - sub_16bit)>, - Requires<[In64BitMode]>; -def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), - (MOVZX32_NOREXrr8 - (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, - Requires<[In64BitMode]>; -def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), - (MOVZX32_NOREXrr8 - (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, - Requires<[In64BitMode]>; def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), (SUBREG_TO_REG (i64 0), -- 2.40.0