From 3315ba73c8150d4fbd1dc4a5a27b4e2a8ccdbdfb Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Tue, 28 Jun 2016 14:33:28 +0000 Subject: [PATCH] Convert more cases to isPositionIndependent(). NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274021 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16HardFloat.cpp | 6 +++--- lib/Target/Mips/Mips16ISelDAGToDAG.cpp | 2 +- lib/Target/Mips/MipsFastISel.cpp | 2 +- lib/Target/Mips/MipsInstrInfo.td | 6 +++--- lib/Target/Mips/MipsLongBranch.cpp | 12 ++++-------- lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 4 ++-- lib/Target/Mips/MipsSEInstrInfo.cpp | 5 ++--- lib/Target/Mips/MipsSubtarget.cpp | 6 +++++- lib/Target/Mips/MipsSubtarget.h | 1 + 9 files changed, 22 insertions(+), 22 deletions(-) diff --git a/lib/Target/Mips/Mips16HardFloat.cpp b/lib/Target/Mips/Mips16HardFloat.cpp index 1e90870b0d1..d2d1c65e40d 100644 --- a/lib/Target/Mips/Mips16HardFloat.cpp +++ b/lib/Target/Mips/Mips16HardFloat.cpp @@ -261,7 +261,7 @@ static std::string swapFPIntParams(FPParamVariant PV, Module *M, bool LE, static void assureFPCallStub(Function &F, Module *M, const MipsTargetMachine &TM) { // for now we only need them for static relocation - if (TM.getRelocationModel() == Reloc::PIC_) + if (TM.isPositionIndependent()) return; LLVMContext &Context = M->getContext(); bool LE = TM.isLittleEndian(); @@ -439,7 +439,7 @@ static bool fixupFPReturnAndCall(Function &F, Module *M, Modified=true; F.addFnAttr("saveS2"); } - if (TM.getRelocationModel() != Reloc::PIC_ ) { + if (!TM.isPositionIndependent()) { if (needsFPHelperFromSig(*F_)) { assureFPCallStub(*F_, M, TM); Modified=true; @@ -453,7 +453,7 @@ static bool fixupFPReturnAndCall(Function &F, Module *M, static void createFPFnStub(Function *F, Module *M, FPParamVariant PV, const MipsTargetMachine &TM) { - bool PicMode = TM.getRelocationModel() == Reloc::PIC_; + bool PicMode = TM.isPositionIndependent(); bool LE = TM.isLittleEndian(); LLVMContext &Context = M->getContext(); std::string Name = F->getName(); diff --git a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 6a4f44354b6..df075a1eea6 100644 --- a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -114,7 +114,7 @@ bool Mips16DAGToDAGISel::selectAddr(bool SPAllowed, SDValue Addr, SDValue &Base, Offset = Addr.getOperand(1); return true; } - if (TM.getRelocationModel() != Reloc::PIC_) { + if (!TM.isPositionIndependent()) { if ((Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress)) return false; diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 946949a4310..19c201d26b2 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -208,7 +208,7 @@ public: bool ISASupported = !Subtarget->hasMips32r6() && !Subtarget->inMicroMipsMode() && Subtarget->hasMips32(); TargetSupported = - ISASupported && (TM.getRelocationModel() == Reloc::PIC_) && + ISASupported && TM.isPositionIndependent() && (static_cast(TM).getABI().IsO32()); UnsupportedFPMode = Subtarget->isFP64bit(); } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index cdd61fd0e2b..0d7abbf7b9f 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -201,8 +201,8 @@ def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, AssemblerPredicate<"FeatureMips16">; def HasCnMips : Predicate<"Subtarget->hasCnMips()">, AssemblerPredicate<"FeatureCnMips">; -def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; -def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">; +def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">; +def RelocPIC : Predicate<"TM.isPositionIndependent()">; def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">, AssemblerPredicate<"!FeatureMips16">; @@ -1854,7 +1854,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6; /// Jump and Branch Instructions def J : MMRel, JumpFJ, FJ<2>, - AdditionalRequires<[RelocStatic]>, IsBranch; + AdditionalRequires<[RelocNotPIC]>, IsBranch; def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6; def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>, diff --git a/lib/Target/Mips/MipsLongBranch.cpp b/lib/Target/Mips/MipsLongBranch.cpp index 8a48d863c8b..8c8faf38396 100644 --- a/lib/Target/Mips/MipsLongBranch.cpp +++ b/lib/Target/Mips/MipsLongBranch.cpp @@ -63,8 +63,7 @@ namespace { public: static char ID; MipsLongBranch(TargetMachine &tm) - : MachineFunctionPass(ID), TM(tm), - IsPIC(TM.getRelocationModel() == Reloc::PIC_), + : MachineFunctionPass(ID), TM(tm), IsPIC(TM.isPositionIndependent()), ABI(static_cast(TM).getABI()) {} const char *getPassName() const override { @@ -187,9 +186,7 @@ void MipsLongBranch::initMBBInfo() { ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End); if ((Br != End) && !Br->isIndirectBranch() && - (Br->isConditionalBranch() || - (Br->isUnconditionalBranch() && - TM.getRelocationModel() == Reloc::PIC_))) + (Br->isConditionalBranch() || (Br->isUnconditionalBranch() && IsPIC))) MBBInfos[I].Br = (++Br).base(); } } @@ -471,8 +468,7 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) { if (STI.inMips16Mode() || !STI.enableLongBranchPass()) return false; - if ((TM.getRelocationModel() == Reloc::PIC_) && - static_cast(TM).getABI().IsO32() && + if (IsPIC && static_cast(TM).getABI().IsO32() && F.getInfo()->globalBaseRegSet()) emitGPDisp(F, TII); @@ -520,7 +516,7 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) { return true; // Compute basic block addresses. - if (TM.getRelocationModel() == Reloc::PIC_) { + if (IsPIC) { uint64_t Address = 0; for (I = MBBInfos.begin(); I != E; Address += I->Size, ++I) diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 95a509a05a2..96bd9cd5c1c 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -163,7 +163,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { return; } - if (MF.getTarget().getRelocationModel() == Reloc::Static) { + if (!MF.getTarget().isPositionIndependent()) { // Set global register to __gnu_local_gp. // // lui $v0, %hi(__gnu_local_gp) @@ -331,7 +331,7 @@ bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, return true; } - if (TM.getRelocationModel() != Reloc::PIC_) { + if (!TM.isPositionIndependent()) { if ((Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress)) return false; diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index 1ccda0bdd5a..841241de66c 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -26,8 +26,7 @@ using namespace llvm; MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) - : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B - : Mips::J), + : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), RI() {} const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { @@ -720,7 +719,7 @@ void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, // addu $sp, $sp, $v1 // jr $ra (via RetRA) const TargetMachine &TM = MBB.getParent()->getTarget(); - if (TM.getRelocationModel() == Reloc::PIC_) + if (TM.isPositionIndependent()) BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9) .addReg(TargetReg) .addReg(ZERO); diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 20915379f96..3e7570ff46e 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -114,7 +114,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, report_fatal_error(ISA + " is not compatible with the DSP ASE", false); } - if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_) + if (NoABICalls && TM.isPositionIndependent()) report_fatal_error("position-independent code requires '-mabicalls'"); // Set UseSmallSection. @@ -126,6 +126,10 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, } } +bool MipsSubtarget::isPositionIndependent() const { + return TM.isPositionIndependent(); +} + /// This overrides the PostRAScheduler bit in the SchedModel for any CPU. bool MipsSubtarget::enablePostRAScheduler() const { return true; } diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 5c428849702..38d3cee7047 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -161,6 +161,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo { std::unique_ptr TLInfo; public: + bool isPositionIndependent() const; /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. bool enablePostRAScheduler() const override; void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; -- 2.50.1