From 32e52f525ad3b389d48f8961c279b5e08ba266a7 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Mon, 22 May 2017 10:14:33 +0000 Subject: [PATCH] Revert r303259 - [globalisel][tablegen] Import rules containing intrinsic_wo_chain. It's causing some buildbots to timeout whenever tablegen needs re-compilation, particularly those with -fsanitize=memory but not only them. A compile time regression was expected since it triples the amount of SelectionDAG rules we are able to import but it's currently too high. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303542 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Target/GlobalISel/SelectionDAGCompat.td | 1 - test/TableGen/GlobalISelEmitter.td | 35 ------------------- utils/TableGen/GlobalISelEmitter.cpp | 25 ++----------- 3 files changed, 3 insertions(+), 58 deletions(-) diff --git a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index 071ec2edb53..a06c67fe814 100644 --- a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -62,7 +62,6 @@ def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; -def : GINodeEquiv; def : GINodeEquiv; // Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern. diff --git a/test/TableGen/GlobalISelEmitter.td b/test/TableGen/GlobalISelEmitter.td index 2784e937954..aeac85962f6 100644 --- a/test/TableGen/GlobalISelEmitter.td +++ b/test/TableGen/GlobalISelEmitter.td @@ -7,10 +7,6 @@ include "llvm/Target/Target.td" def MyTargetISA : InstrInfo; def MyTarget : Target { let InstructionSet = MyTargetISA; } -let TargetPrefix = "mytarget" in { -def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; -} - def R0 : Register<"r0"> { let Namespace = "MyTarget"; } def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>; def GPR32Op : RegisterOperand; @@ -131,37 +127,6 @@ def : Pat<(select GPR32:$src1, complex:$src2, complex:$src3), def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), [(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>; -//===- Test a simple pattern with an intrinsic. ---------------------------===// -// - -// CHECK-LABEL: if ([&]() { -// CHECK-NEXT: MachineInstr &MI0 = I; -// CHECK-NEXT: if (MI0.getNumOperands() < 3) -// CHECK-NEXT: return false; -// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_INTRINSIC) && -// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && -// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && -// CHECK-NEXT: ((/* Operand 1 */ (isOperandImmEqual(MI0.getOperand(1), [[ID:[0-9]+]], MRI)))) && -// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && -// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(2).getReg(), MRI, TRI)))))) { -// CHECK-NEXT: // (intrinsic_wo_chain:i32 [[ID]]:iPTR, GPR32:i32:$src1) => (MOV:i32 GPR32:i32:$src1) -// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MOV)); -// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); -// CHECK-NEXT: MIB.add(MI0.getOperand(2)/*src1*/); -// CHECK-NEXT: for (const auto *FromMI : {&MI0, }) -// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) -// CHECK-NEXT: MIB.addMemOperand(MMO); -// CHECK-NEXT: I.eraseFromParent(); -// CHECK-NEXT: MachineInstr &NewI = *MIB; -// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); -// CHECK-NEXT: return true; -// CHECK-NEXT: } -// CHECK-NEXT: return false; -// CHECK-NEXT: }()) { return true; } - -def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1), - [(set GPR32:$dst, (int_mytarget_nop GPR32:$src1))]>; - //===- Test a nested instruction match. -----------------------------------===// // CHECK-LABEL: if ([&]() { diff --git a/utils/TableGen/GlobalISelEmitter.cpp b/utils/TableGen/GlobalISelEmitter.cpp index dc022fe1ceb..7a500eaf411 100644 --- a/utils/TableGen/GlobalISelEmitter.cpp +++ b/utils/TableGen/GlobalISelEmitter.cpp @@ -1325,27 +1325,8 @@ Expected GlobalISelEmitter::createAndImportSelDAGMatcher( // Match the used operands (i.e. the children of the operator). for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) { - TreePatternNode *SrcChild = Src->getChild(i); - - // For G_INTRINSIC, the operand immediately following the defs is an - // intrinsic ID. - if (SrcGI.TheDef->getName() == "G_INTRINSIC" && i == 0) { - if (!SrcChild->isLeaf()) - return failedImport("Expected IntInit containing intrinsic ID"); - - if (IntInit *SrcChildIntInit = - dyn_cast(SrcChild->getLeafValue())) { - OperandMatcher &OM = - InsnMatcher.addOperand(OpIdx++, SrcChild->getName(), TempOpIdx); - OM.addPredicate(SrcChildIntInit->getValue()); - continue; - } - - return failedImport("Expected IntInit containing instrinsic ID)"); - } - - if (auto Error = - importChildMatcher(InsnMatcher, SrcChild, OpIdx++, TempOpIdx)) + if (auto Error = importChildMatcher(InsnMatcher, Src->getChild(i), OpIdx++, + TempOpIdx)) return std::move(Error); } @@ -1380,7 +1361,7 @@ Error GlobalISelEmitter::importChildMatcher(InstructionMatcher &InsnMatcher, auto OpTyOrNone = MVTToLLT(ChildTypes.front().getConcrete()); if (!OpTyOrNone) - return failedImport("Src operand has an unsupported type (" + to_string(*SrcChild) + ")"); + return failedImport("Src operand has an unsupported type"); OM.addPredicate(*OpTyOrNone); // Check for nested instructions. -- 2.40.0