From 31fd1989fda6e4e563329b5f14f555e59e015db0 Mon Sep 17 00:00:00 2001 From: Aditya Nandakumar Date: Tue, 13 Aug 2019 04:32:33 +0000 Subject: [PATCH] [GlobalISel]: Add KnownBits for G_XOR https://reviews.llvm.org/D66119 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368648 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 13 +++++++++++++ unittests/CodeGen/GlobalISel/KnownBitsTest.cpp | 16 ++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/lib/CodeGen/GlobalISel/GISelKnownBits.cpp index aef43568b63..31e28f5ed5c 100644 --- a/lib/CodeGen/GlobalISel/GISelKnownBits.cpp +++ b/lib/CodeGen/GlobalISel/GISelKnownBits.cpp @@ -131,6 +131,19 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known, Known.Zero.setLowBits(KnownZeroLow); break; } + case TargetOpcode::G_XOR: { + computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, + Depth + 1); + computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, + Depth + 1); + + // Output known-0 bits are known if clear or set in both the LHS & RHS. + APInt KnownZeroOut = (Known.Zero & Known2.Zero) | (Known.One & Known2.One); + // Output known-1 are known to be set if set in only one of the LHS, RHS. + Known.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero); + Known.Zero = KnownZeroOut; + break; + } // G_GEP is like G_ADD. FIXME: Is this true for all targets? case TargetOpcode::G_GEP: case TargetOpcode::G_ADD: { diff --git a/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp b/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp index 2fd09feb1f7..f67184fc208 100644 --- a/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp +++ b/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp @@ -40,6 +40,22 @@ TEST_F(GISelMITest, TestKnownBitsPtrToIntViceVersa) { EXPECT_EQ(256u, Res.One.getZExtValue()); EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue()); } +TEST_F(GISelMITest, TestKnownBitsXOR) { + StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 4\n" + " %4:_(s8) = G_CONSTANT i8 7\n" + " %5:_(s8) = G_XOR %3, %4\n" + " %6:_(s8) = COPY %5\n"; + setUp(MIRString); + if (!TM) + return; + unsigned CopyReg = Copies[Copies.size() - 1]; + MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); + unsigned SrcReg = FinalCopy->getOperand(1).getReg(); + GISelKnownBits Info(*MF); + KnownBits Res = Info.getKnownBits(SrcReg); + EXPECT_EQ(3u, Res.One.getZExtValue()); + EXPECT_EQ(252u, Res.Zero.getZExtValue()); +} TEST_F(GISelMITest, TestKnownBits) { -- 2.40.0