From 3122050e4b04fa2c5eedcd327853990051bebcb5 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 24 Sep 2017 05:24:51 +0000 Subject: [PATCH] [X86] Make sure we still mark the full register as implicitly defined when we shrink 256/512 bit zeroing xors to 128-bit. Not sure if anything really cares, but this seems like the right thing to do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314071 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrInfo.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index abef03c2ea8..4b56807cffc 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -7731,7 +7731,9 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { unsigned SrcReg = MIB->getOperand(0).getReg(); unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); MIB->getOperand(0).setReg(XReg); - return Expand2AddrUndef(MIB, get(X86::VXORPSrr)); + Expand2AddrUndef(MIB, get(X86::VXORPSrr)); + MIB.addReg(SrcReg, RegState::ImplicitDefine); + return true; } case X86::AVX512_128_SET0: case X86::AVX512_FsFLD0SS: @@ -7755,8 +7757,10 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) { unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); MIB->getOperand(0).setReg(XReg); - return Expand2AddrUndef(MIB, - get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); + Expand2AddrUndef(MIB, + get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); + MIB.addReg(SrcReg, RegState::ImplicitDefine); + return true; } return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); } @@ -7766,7 +7770,9 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { if (TRI->getEncodingValue(SrcReg) < 16) { unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); MIB->getOperand(0).setReg(XReg); - return Expand2AddrUndef(MIB, get(X86::VXORPSrr)); + Expand2AddrUndef(MIB, get(X86::VXORPSrr)); + MIB.addReg(SrcReg, RegState::ImplicitDefine); + return true; } return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); } -- 2.49.0