From 2e692a0fecb428c18f91cb743881970e05126851 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 15 Jul 2019 19:39:31 +0000 Subject: [PATCH] AMDGPU/GlobalISel: Fix G_ICMP for wave32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366114 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 4 ++-- test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir | 13 +++++++------ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 317a9b5c08c..5a73b0d1139 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -583,7 +583,7 @@ bool AMDGPUInstructionSelector::selectG_ICMP(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); MachineFunction *MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); - DebugLoc DL = I.getDebugLoc(); + const DebugLoc &DL = I.getDebugLoc(); unsigned SrcReg = I.getOperand(2).getReg(); unsigned Size = RBI.getSizeInBits(SrcReg, MRI, TRI); @@ -616,7 +616,7 @@ bool AMDGPUInstructionSelector::selectG_ICMP(MachineInstr &I) const { .add(I.getOperand(2)) .add(I.getOperand(3)); RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(), - AMDGPU::SReg_64RegClass, MRI); + *TRI.getBoolRC(), MRI); bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); I.eraseFromParent(); return Ret; diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir index 04769922fdc..d2fe30a0845 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir @@ -1,5 +1,6 @@ -# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN -# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN +# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN -DVCCRC=sreg_64_xexec %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN -DVCCRC=sreg_64_xexec %s +# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN -DVCCRC=sreg_32_xm0_xexec %s --- name: icmp_s32_s_mix @@ -129,8 +130,8 @@ regBankSelected: true # GCN: [[VGPR7:%[0-9]+]]:vgpr_32 = COPY $vgpr7 # GCN: [[VGPR8:%[0-9]+]]:vgpr_32 = COPY $vgpr8 # GCN: [[VGPR9:%[0-9]+]]:vgpr_32 = COPY $vgpr9 -# GCN: [[COND0:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[VGPR2]], [[VGPR3]] -# GCN: [[COND1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[VGPR6]], [[VGPR7]] +# GCN: [[COND0:%[0-9]+]]:[[VCCRC]] = V_CMP_NE_U32_e64 [[VGPR2]], [[VGPR3]] +# GCN: [[COND1:%[0-9]+]]:[[VCCRC]] = V_CMP_NE_U32_e64 [[VGPR6]], [[VGPR7]] # GCN: V_CNDMASK_B32_e64 0, [[VGPR9]], 0, [[VGPR8]], [[COND0]] # GCN: V_CNDMASK_B32_e64 0, [[VGPR5]], 0, [[VGPR4]], [[COND1]] @@ -339,8 +340,8 @@ legalized: true regBankSelected: true # GCN-LABEL: name: icmp_eq_ne_p3_vv -# GCN: %2:sreg_64_xexec = V_CMP_EQ_U32_e64 %0, %1, implicit $exec -# GCN: %3:sreg_64_xexec = V_CMP_NE_U32_e64 %0, %1, implicit $exec +# GCN: %2:[[VCCRC]] = V_CMP_EQ_U32_e64 %0, %1, implicit $exec +# GCN: %3:[[VCCRC]] = V_CMP_NE_U32_e64 %0, %1, implicit $exec body: | bb.0: -- 2.40.0