From 2d73fb9e310a46d9dfb36a967d4377367d647c7c Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 21 Jun 2019 16:43:50 +0000 Subject: [PATCH] [AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal. We sometimes get poor code size because constants of types < 32b are legalized as 32 bit G_CONSTANTs with a truncate to fit. This works but means that the localizer can no longer sink them (although it's possible to extend it to do so). On AArch64 however s8 and s16 constants can be selected in the same way as s32 constants, with a mov pseudo into a W register. If we make s8 and s16 constants legal then we can avoid unnecessary truncates, they can be CSE'd, and the localizer can sink them as normal. There is a caveat: if the user of a smaller constant has to widen the sources, we end up with an anyext of the smaller typed G_CONSTANT. This can cause regressions because of the additional extend and missed pattern matching. To remedy this, there's a new artifact combiner to generate the wider G_CONSTANT if it's legal for the target. Differential Revision: https://reviews.llvm.org/D63587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364075 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../GlobalISel/LegalizationArtifactCombiner.h | 21 ++++++++ .../AArch64/AArch64InstructionSelector.cpp | 7 ++- lib/Target/AArch64/AArch64LegalizerInfo.cpp | 4 +- .../AArch64/GlobalISel/legalize-add.mir | 8 +-- .../AArch64/GlobalISel/legalize-atomicrmw.mir | 30 +++++------ .../AArch64/GlobalISel/legalize-cmpxchg.mir | 40 +++++++------- .../AArch64/GlobalISel/legalize-constant.mir | 19 +++---- .../GlobalISel/legalize-load-store.mir | 5 +- .../GlobalISel/legalize-merge-values.mir | 22 ++++---- .../AArch64/GlobalISel/legalize-phi.mir | 54 +++++++++---------- .../GlobalISel/legalize-unmerge-values.mir | 18 ------- .../legalizer-combiner-zext-trunc-crash.mir | 49 ++++++++--------- .../AArch64/GlobalISel/legalizer-combiner.mir | 21 ++++++++ .../AArch64/GlobalISel/select-constant.mir | 32 +++++++++++ .../AMDGPU/GlobalISel/legalize-anyext.mir | 10 ++-- .../X86/GlobalISel/legalize-constant.mir | 10 ++-- 16 files changed, 192 insertions(+), 158 deletions(-) diff --git a/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h index d68704ee623..aa7c0cd860c 100644 --- a/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ b/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -62,6 +62,23 @@ public: markInstAndDefDead(MI, *ExtMI, DeadInsts); return true; } + + // Try to fold aext(g_constant) when the larger constant type is legal. + // Can't use MIPattern because we don't have a specific constant in mind. + auto *SrcMI = MRI.getVRegDef(SrcReg); + if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { + const LLT &DstTy = MRI.getType(DstReg); + if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) { + auto CstVal = SrcMI->getOperand(1); + APInt Val = CstVal.isImm() + ? APInt(DstTy.getSizeInBits(), CstVal.getImm()) + : CstVal.getCImm()->getValue(); + Val = Val.sext(DstTy.getSizeInBits()); + Builder.buildConstant(DstReg, Val); + markInstAndDefDead(MI, *SrcMI, DeadInsts); + return true; + } + } return tryFoldImplicitDef(MI, DeadInsts); } @@ -425,6 +442,10 @@ private: return Step.Action == Unsupported || Step.Action == NotFound; } + bool isInstLegal(const LegalityQuery &Query) const { + return LI.getAction(Query).Action == LegalizeActions::Legal; + } + bool isConstantUnsupported(LLT Ty) const { if (!Ty.isVector()) return isInstUnsupported({TargetOpcode::G_CONSTANT, {Ty}}); diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index d059017da2f..c3da315ba12 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1200,6 +1200,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, case TargetOpcode::G_CONSTANT: { const bool isFP = Opcode == TargetOpcode::G_FCONSTANT; + const LLT s8 = LLT::scalar(8); + const LLT s16 = LLT::scalar(16); const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); const LLT p0 = LLT::pointer(0, 64); @@ -1231,7 +1233,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I, return false; } else { // s32 and s64 are covered by tablegen. - if (Ty != p0) { + if (Ty != p0 && Ty != s8 && Ty != s16) { LLVM_DEBUG(dbgs() << "Unable to materialize integer " << Ty << " constant, expected: " << s32 << ", " << s64 << ", or " << p0 << '\n'); @@ -1246,8 +1248,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I, } } + // We allow G_CONSTANT of types < 32b. const unsigned MovOpc = - DefSize == 32 ? AArch64::MOVi32imm : AArch64::MOVi64imm; + DefSize == 64 ? AArch64::MOVi64imm : AArch64::MOVi32imm; if (isFP) { // Either emit a FMOV, or emit a copy to emit a normal mov. diff --git a/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/lib/Target/AArch64/AArch64LegalizerInfo.cpp index cf063316c7d..741f721acca 100644 --- a/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -279,8 +279,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { // Constants getActionDefinitionsBuilder(G_CONSTANT) - .legalFor({p0, s32, s64}) - .clampScalar(0, s32, s64) + .legalFor({p0, s8, s16, s32, s64}) + .clampScalar(0, s8, s64) .widenScalarToNextPow2(0); getActionDefinitionsBuilder(G_FCONSTANT) .legalFor({s32, s64}) diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/test/CodeGen/AArch64/GlobalISel/legalize-add.mir index 3c2a52b7f0a..8fee0f697db 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-add.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-add.mir @@ -9,8 +9,8 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s8) ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]] ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]] ; CHECK: $x0 = COPY [[UADDE]](s64) @@ -36,8 +36,8 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s8) ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]] ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]] ; CHECK: [[UADDE4:%[0-9]+]]:_(s64), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE3]] diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir b/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir index 71cb9270acc..30897eda815 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir @@ -18,11 +18,10 @@ body: | ; CHECK-LABEL: name: cmpxchg_i8 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[CST2:%[0-9]+]]:_(s8) = G_TRUNC [[CST]] - ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 1 on %ir.addr) - ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] - ; CHECK: $w0 = COPY [[RES2]] + ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 + ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s8) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (load store monotonic 1 on %ir.addr) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ATOMICRMW_ADD]](s8) + ; CHECK: $w0 = COPY [[ANYEXT]](s32) %0:_(p0) = COPY $x0 %1:_(s8) = G_CONSTANT i8 1 %2:_(s8) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 1 on %ir.addr) @@ -38,11 +37,10 @@ body: | ; CHECK-LABEL: name: cmpxchg_i16 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[CST2:%[0-9]+]]:_(s16) = G_TRUNC [[CST]] - ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 2 on %ir.addr) - ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] - ; CHECK: $w0 = COPY [[RES2]] + ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 + ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s16) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (load store monotonic 2 on %ir.addr) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ATOMICRMW_ADD]](s16) + ; CHECK: $w0 = COPY [[ANYEXT]](s32) %0:_(p0) = COPY $x0 %1:_(s16) = G_CONSTANT i16 1 %2:_(s16) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 2 on %ir.addr) @@ -58,9 +56,9 @@ body: | ; CHECK-LABEL: name: cmpxchg_i32 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 4 on %ir.addr) - ; CHECK: $w0 = COPY [[RES]] + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (load store monotonic 4 on %ir.addr) + ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32) %0:_(p0) = COPY $x0 %1:_(s32) = G_CONSTANT i32 1 %2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 4 on %ir.addr) @@ -75,9 +73,9 @@ body: | ; CHECK-LABEL: name: cmpxchg_i64 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 8 on %ir.addr) - ; CHECK: $x0 = COPY [[RES]] + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (load store monotonic 8 on %ir.addr) + ; CHECK: $x0 = COPY [[ATOMICRMW_ADD]](s64) %0:_(p0) = COPY $x0 %1:_(s64) = G_CONSTANT i64 1 %2:_(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr) diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir b/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir index e8a73b71773..d7e2af1c6c9 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir @@ -18,13 +18,11 @@ body: | ; CHECK-LABEL: name: cmpxchg_i8 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[CMPT:%[0-9]+]]:_(s8) = G_TRUNC [[CMP]] - ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[CSTT:%[0-9]+]]:_(s8) = G_TRUNC [[CST]] - ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 1 on %ir.addr) - ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s8) - ; CHECK: $w0 = COPY [[RES2]] + ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 + ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 + ; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s8) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic 1 on %ir.addr) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ATOMIC_CMPXCHG]](s8) + ; CHECK: $w0 = COPY [[ANYEXT]](s32) %0:_(p0) = COPY $x0 %1:_(s8) = G_CONSTANT i8 0 %2:_(s8) = G_CONSTANT i8 1 @@ -41,13 +39,11 @@ body: | ; CHECK-LABEL: name: cmpxchg_i16 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[CMPT:%[0-9]+]]:_(s16) = G_TRUNC [[CMP]] - ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[CSTT:%[0-9]+]]:_(s16) = G_TRUNC [[CST]] - ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 2 on %ir.addr) - ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s16) - ; CHECK: $w0 = COPY [[RES2]] + ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 + ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 + ; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s16) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic 2 on %ir.addr) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ATOMIC_CMPXCHG]](s16) + ; CHECK: $w0 = COPY [[ANYEXT]](s32) %0:_(p0) = COPY $x0 %1:_(s16) = G_CONSTANT i16 0 %2:_(s16) = G_CONSTANT i16 1 @@ -64,10 +60,10 @@ body: | ; CHECK-LABEL: name: cmpxchg_i32 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 4 on %ir.addr) - ; CHECK: $w0 = COPY [[RES]] + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic 4 on %ir.addr) + ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG]](s32) %0:_(p0) = COPY $x0 %1:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 1 @@ -83,10 +79,10 @@ body: | ; CHECK-LABEL: name: cmpxchg_i64 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr) - ; CHECK: $x0 = COPY [[RES]] + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic 8 on %ir.addr) + ; CHECK: $x0 = COPY [[ATOMIC_CMPXCHG]](s64) %0:_(p0) = COPY $x0 %1:_(s64) = G_CONSTANT i64 0 %2:_(s64) = G_CONSTANT i64 1 diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir index 6c20fb701b7..361cea9864c 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir @@ -30,20 +30,17 @@ body: | ; CHECK-LABEL: name: test_constant ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; CHECK: $w0 = COPY [[COPY]](s32) + ; CHECK: $w0 = COPY [[C]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) - ; CHECK: $w0 = COPY [[COPY1]](s32) + ; CHECK: $w0 = COPY [[C1]](s32) ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32) - ; CHECK: $w0 = COPY [[COPY2]](s32) - ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; CHECK: $w0 = COPY [[C3]](s32) - ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32) + ; CHECK: $w0 = COPY [[COPY]](s32) + ; CHECK: $w0 = COPY [[C2]](s32) + ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK: $x0 = COPY [[C3]](s64) + ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: $x0 = COPY [[C4]](s64) - ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; CHECK: $x0 = COPY [[C5]](s64) %0(s1) = G_CONSTANT i1 0 %6:_(s32) = G_ANYEXT %0 $w0 = COPY %6 diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir index 96e043024d4..55e70689920 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir @@ -121,10 +121,9 @@ body: | ; CHECK-LABEL: name: test_store ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) - ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND]](s32) ; CHECK: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store 1) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir b/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir index a9c8ad6cece..2772d62d498 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir @@ -7,21 +7,19 @@ body: | bb.0: ; CHECK-LABEL: name: test_merge_s4 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] - ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 4 + ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C1]](s8) + ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) - ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C3]] - ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32) + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C2]] + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[ZEXT]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) - ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C3]] - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) - ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY1]] + ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C2]] + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) + ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY]] ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32) - ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8) - ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY2]](s8) + ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s8) ; CHECK: $x0 = COPY [[ANYEXT]](s64) %0:_(s64) = G_CONSTANT i64 0 %1:_(s4) = G_TRUNC %0 diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir index 582c0f9c68c..51f61ea773c 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s --- | ; ModuleID = '/tmp/test.ll' @@ -291,26 +292,24 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) + ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 ; CHECK: bb.1: ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) - ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, [[TRUNC2:%[0-9]+]](s16), %bb.1 + ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, %13(s16), %bb.1 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16) - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[COPY1]] + ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[C1]] ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]] + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]] - ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) - ; CHECK: [[TRUNC2]]:_(s16) = G_TRUNC [[ADD]](s32) - ; CHECK: G_BRCOND [[TRUNC1]](s1), %bb.1 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32) + ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1 ; CHECK: bb.2: ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) - ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]] + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] ; CHECK: $w0 = COPY [[AND1]](s32) ; CHECK: RET_ReallyLR implicit $w0 bb.0: @@ -358,18 +357,17 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 ; CHECK: bb.1: ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) - ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, [[COPY1:%[0-9]+]](s16), %bb.1 + ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, %7(s16), %bb.1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16) ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]] - ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) - ; CHECK: [[COPY1]]:_(s16) = COPY [[PHI]](s16) - ; CHECK: G_BRCOND [[TRUNC1]](s1), %bb.1 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) + ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[PHI]](s16) + ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1 ; CHECK: bb.2: ; CHECK: $w0 = COPY [[AND]](s32) ; CHECK: RET_ReallyLR implicit $w0 @@ -429,7 +427,6 @@ body: | ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]] @@ -443,11 +440,11 @@ body: | ; CHECK: G_BR %bb.3 ; CHECK: bb.2: ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C3]](s32) - ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32) + ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 42 + ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32) ; CHECK: bb.3: - ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC4]](s16), %bb.2 - ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC3]](s16), %bb.2 + ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC3]](s16), %bb.2 + ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[C3]](s16), %bb.2 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16) ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]] @@ -534,7 +531,6 @@ body: | ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 44 - ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 43 ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]] @@ -544,15 +540,15 @@ body: | ; CHECK: G_BR %bb.2 ; CHECK: bb.1: ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) - ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.0, [[TRUNC4:%[0-9]+]](s16), %bb.1 - ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.0, %21(s16), %bb.1 + ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C5]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]] ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]] ; CHECK: [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[PHI]](s16) - ; CHECK: [[TRUNC4]]:_(s16) = G_TRUNC [[C4]](s32) + ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 43 ; CHECK: G_BRCOND [[TRUNC3]](s1), %bb.2 ; CHECK: G_BR %bb.1 ; CHECK: bb.2: diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir b/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir index 39198da0ec2..a084e0e9be6 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir @@ -8,24 +8,6 @@ name: test_unmerge_s4 body: | bb.0: ; CHECK-LABEL: name: test_unmerge_s4 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) - ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s8) - ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) - ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16) - ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s16) - ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT1]](s32) - ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) - ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s16) - ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16) - ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT1]], [[ANYEXT2]] - ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32) - ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC3]](s16) - ; CHECK: [[TRUNC4:%[0-9]+]]:_(s4) = G_TRUNC [[UV]](s8) - ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC4]](s4) - ; CHECK: [[TRUNC5:%[0-9]+]]:_(s4) = G_TRUNC [[UV1]](s8) - ; CHECK: $x0 = COPY [[ANYEXT3]](s64) %0:_(s8) = G_CONSTANT i8 0 %1:_(s4), %2:_(s4)= G_UNMERGE_VALUES %0 %3:_(s64) = G_ANYEXT %1 diff --git a/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir b/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir index 391170c2dca..e41b6e142d6 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir @@ -10,42 +10,37 @@ body: | ; CHECK-LABEL: name: zext_trunc_dead_inst_crash ; CHECK: bb.0: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 46 - ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -33 - ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65 - ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 26 + ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 46 + ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 26 ; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF ; CHECK: bb.1: ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI %33(s16), %bb.2, [[DEF]](s16), %bb.0 - ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI %32(s16), %bb.2, [[DEF]](s16), %bb.0 + ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]] - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]] - ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]] - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]] + ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s8) + ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[ZEXT]] + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF - ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[DEF1]] - ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32) - ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[COPY2]] - ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND2]](s32) - ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32) - ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY4]] - ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) - ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]] - ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32) - ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]] - ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND3]](s32), [[AND4]] - ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR]](s32) - ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY7]], [[COPY8]] + ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[DEF1]] + ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -33 + ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]] + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND1]](s32) + ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65 + ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C4]] + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]] + ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[C1]](s8) + ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[ZEXT1]] + ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) + ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32) + ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[OR1]](s32) ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.2 ; CHECK: bb.2: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 - ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C5]](s32) + ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 64 ; CHECK: G_BR %bb.1 bb.1: %1:_(s8) = G_CONSTANT i8 46 diff --git a/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir b/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir index b0744504145..cad818777e2 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir @@ -8,6 +8,7 @@ entry: ret void } + define void @test_legal_const_ext() { ret void } ... --- @@ -23,3 +24,23 @@ body: | %2:_(s32), %3:_(s32), %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %1(<4 x s32>) $w0 = COPY %2(s32) ... + +--- +name: test_legal_const_ext +body: | + bb.1: + liveins: $w0 + ; CHECK-LABEL: name: test_legal_const_ext + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C]] + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK: $w0 = COPY [[COPY2]](s32) + %0:_(s32) = COPY $w0 + %1:_(s1) = G_TRUNC %0(s32) + %2:_(s1) = G_CONSTANT i1 2 + %3:_(s1) = G_ADD %1(s1), %2(s1) + %4:_(s32) = G_ANYEXT %3(s1) + $w0 = COPY %4(s32) +... diff --git a/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/test/CodeGen/AArch64/GlobalISel/select-constant.mir index 234957a8f8e..2b9d51924d3 100644 --- a/test/CodeGen/AArch64/GlobalISel/select-constant.mir +++ b/test/CodeGen/AArch64/GlobalISel/select-constant.mir @@ -4,6 +4,8 @@ --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + define i8 @const_s8() { ret i8 42 } + define i16 @const_s16() { ret i16 42 } define i32 @const_s32() { ret i32 42 } define i64 @const_s64() { ret i64 1234567890123 } @@ -13,6 +15,36 @@ define double @fconst_s64_0() { ret double 0.0 } ... +--- +name: const_s8 +legalized: true +regBankSelected: true +body: | + bb.0: + ; CHECK-LABEL: name: const_s8 + ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]] + ; CHECK: $w0 = COPY [[COPY]] + %0:gpr(s8) = G_CONSTANT i8 42 + %1:gpr(s32) = G_ANYEXT %0(s8) + $w0 = COPY %1(s32) +... + +--- +name: const_s16 +legalized: true +regBankSelected: true +body: | + bb.0: + ; CHECK-LABEL: name: const_s16 + ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]] + ; CHECK: $w0 = COPY [[COPY]] + %0:gpr(s16) = G_CONSTANT i16 42 + %1:gpr(s32) = G_ANYEXT %0(s16) + $w0 = COPY %1(s32) +... + --- name: const_s32 legalized: true diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir index a7b202a3b0a..b5b3269fc0d 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir @@ -54,9 +54,8 @@ body: | bb.0: ; CHECK-LABEL: name: test_anyext_s1_to_s32 - ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s1) - ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK: $vgpr0 = COPY [[C]](s32) %0:_(s1) = G_CONSTANT i1 0 %1:_(s32) = G_ANYEXT %0 $vgpr0 = COPY %1 @@ -68,9 +67,8 @@ body: | bb.0: ; CHECK-LABEL: name: test_anyext_s1_to_s64 - ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s1) - ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64) + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64) %0:_(s1) = G_CONSTANT i1 0 %1:_(s64) = G_ANYEXT %0 $vgpr0_vgpr1 = COPY %1 diff --git a/test/CodeGen/X86/GlobalISel/legalize-constant.mir b/test/CodeGen/X86/GlobalISel/legalize-constant.mir index a5d3c908751..3b4bec6978f 100644 --- a/test/CodeGen/X86/GlobalISel/legalize-constant.mir +++ b/test/CodeGen/X86/GlobalISel/legalize-constant.mir @@ -18,9 +18,8 @@ registers: body: | bb.1 (%ir-block.0): ; X32-LABEL: name: test_constant - ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8) - ; X32: $eax = COPY [[ANYEXT]](s32) + ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; X32: $eax = COPY [[C]](s32) ; X32: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 8 ; X32: $al = COPY [[C1]](s8) ; X32: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 16 @@ -33,9 +32,8 @@ body: | ; X32: $rax = COPY [[MV]](s64) ; X32: RET 0 ; X64-LABEL: name: test_constant - ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8) - ; X64: $eax = COPY [[ANYEXT]](s32) + ; X64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; X64: $eax = COPY [[C]](s32) ; X64: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 8 ; X64: $al = COPY [[C1]](s8) ; X64: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 16 -- 2.50.1